US 2021/0064541 A1Published application

Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative

AssigneeMicrosoft Technology Licensing, LLC

InventorsVignyan Reddy KOTHINTI NARESH, Arthur PERAIS, Rami Mohammad AL SHEIKH, Shivam PRIYADARSHI

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Abstract

Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative is disclosed. The updating of at least one cache state in the cache memory resulting from a data request is deferred until the data request becomes non-speculative. Thus, a cache state in the cache memory is not updated for requests resulting from mispredictions. Deferring the updating of a cache state in the cache memory can include deferring the storing of received speculative requested data in the main data array of the cache memory as a result of a cache miss until the data request becomes non-speculative. The received speculative requested data can first be stored in a speculative buffer memory associated with a cache memory, and then stored in the main data array if the data request becomes non-speculative.

Claims35

Dependent claims

A non-speculative cache memory in a processor-based system, comprising:

a main data array comprising a plurality of cache entries each configured to store cache data associated with a memory address in a memory system of the processor-based system;
a speculative buffer memory comprising a plurality of buffer entries each comprising a data entry configured to store cached data associated with a memory address in the memory system;
and
a cache controller configured to:
receive a data request from a requestor comprising a target address and an instruction identification (ID) identifying a load instruction comprising the target address processed by a processor in the processor-based system;
search for a cache entry in the main data array associated with the target address of the data request;
search the speculative buffer memory for a buffer entry associated with the target address of the data request;
send a data response to the data request to the requestor based on cache data in the main data array being associated with the target address and cache data in a buffer entry in the speculative buffer memory being associated with the target address;
receive a commit indicator comprising an instruction ID of an instruction that is non-speculative;
and
in response to the received instruction ID in the commit indicator indicating the load instruction of the data request is non-speculative:
update a cache state of a cache entry in the main data array associated with the target address of the data request.

9 more elements

A method of updating a cache state in a non-speculative cache memory in a processor-based system, comprising:

receiving a data request from a requestor comprising a target address and an instruction identification (ID) identifying a load instruction comprising the target address processed by a processor in the processor-based system;
searching a main data array for a cache entry associated with the target address of the data request among a plurality of cache entries each configured to store cache data associated with a memory address in a memory system of the processor-based system;
searching a speculative buffer memory for a buffer entry associated with the target address of the data request among a plurality of buffer entries each configured to store cache data associated with a memory address in the memory system;
sending a data response to the data request to the requestor based on a cache entry in the main data array being associated with the target address and a cache data in a buffer entry in the speculative buffer memory being associated with the target address;
receiving a commit indicator comprising an instruction ID of an instruction that is non-speculative;
and
updating a cache state of a cache entry in the main data array associated with the target address of the data request, in response to the received instruction ID in the commit indicator indicating the load instruction of the data request is non-speculative.

4 more elements

Dependencies are inferred from the claim text.