Optimizing access to page table entries in processor-based devices

A method for optimizing access to page table entries, comprising:

• receiving, by an instruction decode stage of an execution pipeline of a processing element (PE) of a processor-based device, a memory access instruction comprising a virtual memory address;
• determining, by a page table walker circuit of the PE based on the memory access instruction, a number T of page table walk levels to traverse, wherein T is greater than zero (0) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address;
• performing, by the page table walker circuit of the PE based on the virtual memory address, a page table walk of T page table walk levels of a multilevel page table;
• identifying, based on the page table walk, a physical memory address corresponding to a page table entry of the Tth page table walk level;
• and
• performing a memory access operation indicated by the memory access instruction using the physical memory address.

A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to:

• receive a memory access instruction comprising a virtual memory address;
• determine, based on the memory access instruction, a number T of page table walk levels to traverse, wherein T is greater than zero (0) and less than or equal to a number of page table walk levels required to fully translate the virtual memory address;
• perform, based on the virtual memory address, a page table walk of T page table walk levels of a multilevel page table;
• identify, based on the page table walk, a physical memory address corresponding to a page table entry of the Tth page table walk level;
• and
• perform a memory access operation indicated by the memory access instruction using the physical memory address.