Operation cache compression
AssigneeArm Limited
InventorsMichael Brian SCHINZLER, Michael FILIPPO
Life of this patent
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Abstract
A data processing apparatus is provided. The data processing apparatus includes fetch circuitry to fetch instructions from storage circuitry. Decode circuitry decodes each of the instructions into one or more operations and provides the one or more operations to one or more execution units. The decode circuitry is adapted to decode at least one of the instructions into a plurality of operations. Cache circuitry caches the one or more operations and at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations.
Claims16
A data processing apparatus comprising:
- fetch circuitry to fetch instructions from storage circuitry;
- decode circuitry to decode each of the instructions into one or more operations and to provide the one or more operations to one or more execution units, wherein the decode circuitry is adapted to decode at least one of the instructions into a plurality of operations;
- and
- cache circuitry to cache the one or more operations,
- wherein at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations.
A data processing method comprising:
- fetching instructions from storage circuitry;
- decoding each of the instructions into one or more operations, wherein the decoding decodes at least one of the instructions into a plurality of operations;
- providing the one or more operations to one or more execution units;
- and
- caching the one or more operations in cache circuitry,
- wherein at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations.
A data processing apparatus comprising:
- means for fetching instructions from storage circuitry;
- means for decoding each of the instructions into one or more operations, wherein the decoding decodes at least one of the instructions into a plurality of operations;
- means for providing the one or more operations to one or more execution units;
- and
- means for caching the one or more operations,
- wherein at least one entry of the means for caching is a compressed entry that represents the plurality of operations.
Dependencies are inferred from the claim text.