Software-defined coherent caching of pooled memory

A compute platform comprising:

• a central processing unit (CPU) having one or more cores on which software is executed including a plurality of software applications;
• memory coupled to CPU into which software is loaded;
• hardware-based logic, either embedded on a System on a Chip (SoC) including the CPU or implemented in a discrete device coupled to the CPU;
• a network interface including one or more ports configured to be coupled to a network or fabric via which disaggregated memory is accessed;
• wherein execution of a portion of the software programs the hardware-based logic to implement, for each of one or more of the plurality of software applications, a software-defined caching policy to effect caching of at least a portion of an address space in the disaggregated memory allocated for the software application, and wherein data are cached in one or more disaggregated memory (DM) caches embedded on the SoC or embedded on the discrete device.

A network interface controller (NIC), configured to be installed in or attached to a compute platform, comprising:

• one or more ports, configured to be connected to a network or fabric via which one or more pooled memory devices comprising disaggregated memory (DM) are accessed;
• an input/output (I/O) interface, configured to coupled to a central processing unit (CPU) of the compute platform;
• at least one distributed memory (DM) cache;
• hardware based logic to, for each of one or more software applications running on the compute platform, implement a caching policy to effect caching of disaggregated memory in an associated DM cache of at least a portion of an address space allocated for the software application in the disaggregated memory.