Instruction level tracing for analyzing processor failure

A system comprising:

• a memory;
• and
• a processor coupled with the memory, the processor configured to perform a method for instruction-level tracing for analyzing a processor failure, the method comprising:
• detecting a failure during operation of a processor circuit;
• parsing a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure;
• generating a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace;
• performing a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times;
• and
• using the workload for debugging the failure based on the commit ratio being above a predetermined threshold.

A computer program product comprising a computer-readable storage medium having program instructions embodied therewith, the program instructions executable by a processing circuit to perform a method for instruction-level tracing for analyzing a processor failure, the method comprising:

• detecting a failure during operation of a processor circuit;
• parsing a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure;
• generating a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace;
• performing a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times;
• and
• using the workload for debugging the failure based on the commit ratio being above a predetermined threshold.