Restartable cache write-back and invalidation
AssigneeIntel Corporation
InventorsGideon GERZON, Dror CASPI, Arie AHARON, Ido OUZIEL
Life of this patent
Estimating the term…
Abstract
A processor includes a global register to store a value of an interrupted block count. A processor core, communicably coupled to the global register, may, upon execution of an instruction to flush blocks of a cache that are associated with a security domain: flush the blocks of the cache sequentially according to a flush loop of the cache; and in response to detection of a system interrupt: store a value of a current cache block count to the global register as the interrupted block count; and stop execution of the instruction to pause the flush of the blocks of the cache. After handling of the interrupt, the instruction may be called again to restart the flush of the cache.
Claims20
A processor comprising:
- a secure data store to store an indicator of an interrupted block count;
- and
- a processor core communicably coupled to the secure data store, the processor core to, upon execution of an instruction to flush blocks of a cache associated with a security domain:
- flush the blocks of the cache sequentially according to a flush loop of the cache;
- during each iteration of the flush loop, store an indicator of a current cache block count in the secure data store;
- and
- in response to detection of a system interrupt:
- stop execution of the instruction to pause the flush of the blocks of the cache;
- and
- in response to the pause, the indicator of the current cache block count in the secure data store is the indicator of the interrupt block count.
A system comprising:
- a cache to store data read from a memory device;
- a secure data store to store an indicator of an interrupted block count;
- and
- a processor comprising a processor core, the processor core, upon execution of an instruction to flush blocks of the cache associated with a first trust domain, to:
- flush the blocks of the cache sequentially according to a flush loop of the cache;
- store an indicator of a current cache block count, at each iteration of the flush loop, into the secure data store;
- detect a system interrupt;
- and
- stop execution of the instruction to pause the flush of the cache in response to the system interrupt.
A method comprising:
- executing, by a processor, an instruction to flush blocks of a cache associated with a first trust domain;
- initializing, by the processor during execution of the instruction, an indicator of a current cache block count;
- and
- iteratively, by the processor, over a flush loop of the cache:
- flushing a cache block associated with the indicator of the current cache block count;
- incrementing the indicator of the current cache block count;
- determining whether the indicator of the current cache block count corresponds to a total of the cache blocks of the cache;
- detecting whether an interrupt is pending;
- and
- in response to detecting a system interrupt is pending:
- stopping execution of the instruction to pause the flush of the cache;
- and
- storing the indicator of the current cache block count into protected hardware storage as an interrupted block count.
Dependencies are inferred from the claim text.