US 2021/0064075 A1 · CLOCK DISTRIBUTION NETWORK AND METHOD FOR DYNAMICALLY CHANGING A CLOCK FREQUENCY IN A DIGITAL PROCESSING SYSTEM

Abstract

Clock distribution network and method for dynamically changing clock frequency in digital processing system are provided. The method includes receiving, at a first clock input of a first divider, a frequency signal from a clock source and receiving, at a state machine, a first status signal from the first divider, the first status signal indicating a first number of clock edges that have transpired from a first phase reference clock edge of the first divider. The method includes asserting, using the state machine, a first hold signal at a first hold input of the first divider, the first hold signal suspending operation of the first divider when asserted and after asserting the first hold signal, latching a new first divider value into the first divider. The method includes de-asserting, using the state machine, the first hold signal subsequent to latching the new first divider value into the first divider.

Claims20

Dependent claims

A clock distribution network for changing a clock frequency within a digital processing system, the clock distribution network comprising:

a clock source providing a frequency signal;
a first divider including
a first clock input for receiving the frequency signal,
a first hold input for receiving a first hold signal that suspends operation of the first divider when asserted, and
a first status output for providing a first status signal indicating a first number of clock edges that have transpired from a first phase reference clock edge of the first divider;
and
a state machine configured to
receive the first status signal,
assert the first hold signal when the first number of clock edges reaches a first threshold divider count value associated with the first divider,
after the first hold signal is asserted, latch a new first divider value into the first divider, and
de-assert the first hold signal subsequent to latching the new first divider value into the first divider.

8 more elements

A method for changing a clock frequency within a digital processing system, the method comprising:

receiving, at a first clock input of a first divider, a frequency signal from a clock source;
receiving, at a state machine, a first status signal from the first divider, the first status signal indicating a first number of clock edges that have transpired from a first phase reference clock edge of the first divider;
asserting, using the state machine, a first hold signal at a first hold input of the first divider, the first hold signal suspending operation of the first divider when asserted;
after asserting the first hold signal, latching a new first divider value into the first divider;
and
de-asserting, using the state machine, the first hold signal subsequent to latching the new first divider value into the first divider.

3 more elements

Dependencies are inferred from the claim text.

Clock distribution network and method for dynamically changing a clock frequency in a digital processing system

Life of this patent

Clock distribution network and method for dynamically changing a clock frequency in a digital processing system

Life of this patent

Abstract

Claims20