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US 2021/0005232 A1Published application
Sram with local bit line, input/output circuit, and global bit line
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAtul Katoch, Ali Taghvaei
Life of this patent
Estimating the term…
Abstract
A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.
Claims20
An SRAM memory device, comprising:
- a memory array including an SRAM memory cell and a local bit line;
- a local IO circuit having a sense amplifier coupled to the local bit line and configured to generate a local IO signal based on a data signal received on the local bit line, and output a global bit line signal based on the local IO signal to a global bit line, the local IO including a latch circuit having an input terminal connected to the global bit line, wherein the latch circuit is configured to latch the global bit line signal in response to the local IO signal;
- a global IO circuit coupled to the global bit line and configured to receive the latched global bit line signal and output a global IO signal.
A method, comprising:
- receiving a data signal from a memory cell;
- generating a local IO signal based on the data signal;
- outputting a global bit line signal based on the local IO signal to a global bit line;
- receiving the local IO signal by an enable terminal of a latch circuit;
- and
- latching the global bit line signal on the global bit line in response to the local IO signal received by the enable terminal of the latch circuit.
3 more elements
A memory device, comprising:
- a first memory array including a first memory cell and a first local bit line;
- a first local IO circuit connected to the first local bit line and configured to generate a first local IO signal based on a first data signal received on the first local bit line, and output a first global bit line signal based on the first local IO signal to a first global bit line;
- a first local latch circuit having an input terminal connected to the first global bit line and an enable terminal connected to receive the first local IO signal, wherein the latch circuit is configured to latch the first global bit line signal in response to the first local IO signal;
- a first global IO circuit connected to the first global bit line and configured to output a first global IO signal based on the first global bit line signal;
- a second memory array including a second memory cell and a second local bit line;
- a second local IO circuit connected to the second local bit line and configured to generate a second local IO signal based on a second data signal received on the second local bit line, and output a second global bit line signal based on the second local IO signal to a second global bit line;
- a second local latch circuit having an input terminal connected to the second global bit line and an enable terminal connected to receive the second local IO signal, wherein the second local latch circuit is configured to latch the second global bit line signal in response to the second local IO signal;
- and
- a second global IO circuit connected to the second global bit line and configured to output a second global IO signal based on the second global bit line signal.
6 more elements
Dependencies are inferred from the claim text.