# US 2021/0004667 A1 · Operation processing apparatus and operation processing method

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- Number: US 2021/0004667 A1
- Document ID: US20210004667A1
- Status: Published application
- Kind: A1
- Application number: 16/916,507
- Filed: 2020-06-30
- Published: 2021-01-07
- Earliest claimed: 2019-07-01
- Assignees: Canon Kabushiki Kaisha
- Applicants: Canon Kabushiki Kaisha
- Inventors: Shiori Wakino
- Web page: https://patentgrep.com/patent/US20210004667A1

## CPC

- G06N 3/063: using electronic means
- G06N 3/045: Combinations of networks
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06T 1/60: Memory management
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL

## Abstract

An apparatus for, by inputting data to a hierarchical neural network and performing operation processing in each layer of the network, calculating a feature plane in the layer, comprises an operation unit, a feature plane holding unit including at least one memory that holds a feature plane to be processed, a unit configured to control to arrange the feature plane in the memory based on network information as information about each layer undergoing the operation processing and to manage reading/writing from/in the memory, and a processor configured to access, via a bus, the feature plane holding unit which is address-mapped in a memory space. The processor calculates, based on the network information, an address address-mapped in the memory space, reads out the feature plane, and processes the feature plane.

## Claims

### Claim 1

An operation processing apparatus for, by inputting input data to a hierarchical neural network and performing operation processing in each layer of the hierarchical neural network, calculating a feature plane in the layer, comprising:
an operation unit;
a feature plane holding unit including at least one memory that holds a feature plane to be processed by the operation unit;
a memory access management unit configured to control to arrange the feature plane in the memory based on network information as information about each layer undergoing the operation processing and to manage reading/writing from/in the memory; and
a processor configured to access, via a bus, the feature plane holding unit which is address-mapped in a memory space,
wherein the processor calculates, based on the network information, an address address-mapped in the memory space, reads out the feature plane, and processes the feature plane.

### Claim 2 (depends on 1)

The apparatus according to claim 1, wherein the network information of the layer includes a number of the layer, a horizontal size and a vertical size of each feature plane, and the number of feature planes.

### Claim 3 (depends on 1)

The apparatus according to claim 1, wherein the memory stores a feature plane of one of an intermediate layer and a final layer among the layers, and the processor processes the feature plane of one of the intermediate layer and the final layer.

### Claim 4 (depends on 1)

The apparatus according to claim 1, wherein the processor calculates the address based on the network information and information of the memory access management unit.

### Claim 5 (depends on 1)

The apparatus according to claim 1, wherein the feature plane in the feature plane holding unit is interleaved in a plurality of memories on a layer basis.

### Claim 6 (depends on 1)

The apparatus according to claim 1, wherein the feature plane in the feature plane holding unit is interleaved in a plurality of memories on a line basis.

### Claim 7 (depends on 1)

The apparatus according to claim 1, wherein the memory access management unit calculates a storage destination of the memory based on an access request address of the processor, reads out data, and returns the data.

### Claim 8

An operation processing method for an operation processing apparatus that, by inputting input data to a hierarchical neural network and performing operation processing in each layer of the hierarchical neural network, calculates a feature plane in the layer, wherein
the operation processing apparatus includes
an operation unit,
a feature plane holding unit including at least one memory that holds a feature plane to be processed by the operation unit,
a memory access management unit configured to control to arrange the feature plane in the memory based on network information as information about each layer undergoing the operation processing and to manage reading/writing from/in the memory, and
a processor configured to access, via a bus, the feature plane holding unit which is address-mapped in a memory space, and
the processor calculates, based on the network information, an address address-mapped in the memory space, reads out the feature plane, and processes the feature plane.