Integrated circuit design method and non-transitory computer readable medium thereof
AssigneeRealtek Semiconductor Corp.
InventorsI-Ching TSAI, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
Life of this patent
Estimating the term…
Loading patent…
AssigneeRealtek Semiconductor Corp.
InventorsI-Ching TSAI, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
Estimating the term…
An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.
An integrated circuit (IC) design method, comprising:
A non-transitory computer readable medium that comprises a plurality of computer readable commands, wherein the computer readable commands are executed by a processor of a computer system to execute an IC design method, the IC design method comprising:
Dependencies are inferred from the claim text.