Approximate data bus inversion technique for latency sensitive applications

A system, comprising:

• a processor;
• a first device coupled to the processor;
• and
• a plurality of lanes including first lanes and second lanes, the plurality of lanes to connect the first device to a second device, wherein the first device is to:
• obtain original data comprising first bits and second bits to be transmitted in a new clock cycle, wherein the first bits are to be transmitted via the first lanes, respectively, and the second bits are to be transmitted via the second lanes, respectively;
• determine whether a first criterion associated with the first bits is met;
• determine whether a second criterion associated with the second bits is met;
• and
• transmit an inverted version of the original data via the plurality of lanes in response to, at least in part, determining that the first criterion is met and that the second criterion is met.

A method comprising:

• obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, wherein the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, respectively, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes, respectively;
• determining whether a first criterion associated with the first bits is met;
• determining whether a second criterion associated with the second bits is met;
• and
• determining whether to transmit an inverted version of the original data via the plurality of lanes based, at least in part, on determining whether the first criterion is met and whether the second criterion is met.