Pasid based routing extension for scalable iov systems

A system, comprising:

• a host central processing unit (CPU) having a plurality of cores and a memory controller;
• host memory, coupled to the memory controller on the host CPU;
• a smart controller, coupled to the CPU and having local memory embedded thereon or coupled to local memory;
• a helper device, coupled to the smart controller and-implementing a first Process Address Space Identifier (PASID) associated with a first memory space and a second PASID associated with a second memory space in which data are stored;
• wherein the system is configured to,
• employ the first PASID to fetch a descriptor in the first memory space;
• and
• employ the second PASID to fetch data in the second memory space.

A system, comprising:

• a host central processing unit (CPU) having a plurality of cores, a memory controller, and an input-output memory management unit (IOMMU);
• host memory, coupled to the memory controller on the host CPU;
• an accelerator, coupled to the CPU and having local memory embedded thereon or coupled to local memory;
• an Input/Output Virtualization (IOV) device, operatively coupled to the accelerator and the host CPU controller and including an Assignable Device Interface (ADI) implementing a Control Process Address Space Identifier (C-PASID) associated with a first memory space in the host memory and a Data PASID (D-PASID) associated with a second memory space in the local memory of the accelerator;
• wherein the system is configured to,
• employ the C-PASID to fetch a descriptor in the first memory space;
• and
• employ the D-PASID to fetch data in the second memory space.