Fail information control circuit, semiconductor apparatus including the same, and fail information control method of semiconductor apparatus
AssigneeSK hynix Inc.
InventorJae Yong KANG
Life of this patent
Estimating the term…
Abstract
A fail information control circuit may include: a comparison circuit configured to generate a comparison result signal by comparing read data and write data; a fail bit discrimination circuit configured to generate a first fail discrimination signal for discriminating a fail detected when the write data has a first value and a second fail discrimination signal for discriminating a fail detected when the write data has a second value, in response to the comparison result signal; and a fail bit counter configured to generate a first counting signal by counting the first fail discrimination signal and generate a second counting signal by counting the second fail discrimination signal.
Claims18
A fail information control circuit comprising:
- a comparison circuit configured to generate a comparison result signal by comparing read data and write data;
- a fail bit discrimination circuit configured to:
- generate a first fail discrimination signal for discriminating a fail detected when the write data has a first value;
- and
- generate a second fail discrimination signal for discriminating a fail detected when the write data has a second value, in response to the comparison result signal;
- and
- a fail bit counter configured to generate a first counting signal by counting the first fail discrimination signal and generate a second counting signal by counting the second fail discrimination signal.
A fail information control circuit comprising:
- a comparison circuit configured to generate a comparison result signal by comparing read data and write data;
- a fail bit discrimination circuit configured to generate a first fail discrimination signal for discriminating a fail detected when the write data has a first value and a second fail discrimination signal for discriminating a fail detected when the write data has a second value, in response to the comparison result signal;
- and
- a fail information output circuit configured to:
- generate a first counting signal and a second counting signal by counting the first fail discrimination signal and the second fail discrimination signal;
- and
- generate a first counting correction signal and a second counting correction signal by resetting remaining bits, except for a most significant bit of a first level among bits of the first counting signal and the second counting signal.
A semiconductor apparatus comprising:
- a memory area;
- input/output pads;
- and
- a fail information control circuit configured to:
- classify fails, which are detected according to a result of comparing write data provided to the memory area with read data outputted from the memory area, into a case where write data has a first value and a case where the write data has a second value;
- and
- count the classified fails to generate a first counting signal and a second counting signal,
- wherein the first counting signal and the second counting signal are outputted to an exterior through the input/output pads.
A fail information control method of a semiconductor apparatus, the method comprising:
- a comparison step of comparing read data and write data;
- a counting step of classifying a type of fail bits into a first fail and a second fail when the write data and the read data do not coincide with each other in the comparison step, and generating a first counting signal and a second counting signal;
- and
- an output step of outputting the first counting signal and the second counting signal to an exterior of the semiconductor apparatus.
Dependencies are inferred from the claim text.