Pipeline flattener with conditional triggers
AssigneeTexas Instruments Incorporated
InventorsMarkus Koesler, Johann Zipperer, Christian Wiencke, Wolfgang Lutsch
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Abstract
A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.
Claims20
A device comprising:
- a set of instruction processing stages each configured to process a respective instruction;
- sets of trigger logic coupled to the set of instruction processing stages such that each instruction processing stage is coupled to a respective set of trigger logic, wherein each of the sets of trigger logic is configured to:
- receive a respective condition;
- compare the respective instruction of the respective instruction processing stage to the respective condition;
- and
- determine whether to assert a respective trigger value based on the comparison of the respective instruction to the respective condition.
A processor comprising:
- a pipeline that includes a set of processing stages, wherein the pipeline is configured to:
- receive an instruction;
- process the instruction using the set of processing stages to produce a processed instruction;
- and
- provide the processed instruction;
- and
- sets of debug trigger logic coupled to the stages of the set of processing stages, wherein each of the sets of debug trigger logic is configured to:
- receive a respective condition;
- compare the instruction at a respective stage of the set of processing stages to the respective condition;
- and
- determine whether to assert a respective debug trigger value based on the comparison of the respective instruction to the respective condition.
A method comprising:
- receiving an instruction;
- performing a set of operations on the instruction using a set of instruction processing stages;
- and
- for each stage of the set of instruction processing stages:
- comparing the instruction to a respective condition;
- determining whether to assert a trigger value associated with the respective stage based on the comparing of the instruction to the respective condition.
Dependencies are inferred from the claim text.