Branch target buffer arrangement for instruction prefetching
AssigneeThe University Court of the University of Edinburgh
InventorsRakesh Kumar, Boris Grot, Vijay Nagarajan
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AssigneeThe University Court of the University of Edinburgh
InventorsRakesh Kumar, Boris Grot, Vijay Nagarajan
Estimating the term…
A branch target buffer, BTB, is provided to store at least one BTB entry corresponding to a respective branch in a control flow in a sequence of machine-readable instructions of a computer program. The BTB has a tag field to compare with a program counter of a fetch address generator and at least one further field to store information characteristic of the branch instruction identified by the corresponding tag field and allowing a conditional branch to be distinguished from an unconditional branch instruction. The BTB has a predetermined storage capacity and is utilized such that unconditional branch instructions are preferentially allocated storage space in the BTB relative to conditional branch instructions.
1-28. (canceled)
A branch target buffer, BTB, to store at least one BTB entry corresponding to a respective branch in a control flow in a sequence of machine-readable instructions of a computer program, the BTB entry comprising:
A method of buffering branch instructions in a branch target buffer, BTB, of a data processing apparatus, the method comprising:
Machine-readable instructions provided on a non-transitory medium, the instructions upon execution to cause at least one processor to:
Dependencies are inferred from the claim text.