Memory system and operating method thereof
AssigneeSK hynix Inc.
InventorsJoo-Young LEE, Hoe-Seung Jung
Life of this patent
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Abstract
A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.
Claims20
A memory system, comprising:
- a memory device;
- a first queue suitable for queuing commands received from a host;
- a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme;
- and
- a processor suitable for:
- delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue;
- and
- determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.
A method for operating a memory system, comprising:
- queuing commands received from a host into a first queue;
- enqueuing the commands from the first queue into a second queue and dequeuing the commands to a memory device according to the FIFO scheme;
- when a logical address corresponding to a write command, in response to which a program operation is being performed, is the same as a logical address of a read command enqueued in the first queue, delaying enqueuing the read command into the second queue until the program operation is successfully performed;
- and
- determining whether or not to enqueue a subsequent read command which is enqueued in the first queue behind the read command into the second queue, when the enqueuing of the read command into the second queue is delayed.
Dependencies are inferred from the claim text.