Multi-Die System Capable of Sharing Non-volatile Memory

A method of operating a multi-die system in a chip, the chip comprising a first die, a second die and an arbiter, the method comprising:

• generating, by a first processor in the first die, a first control signal to a first access controller of the first die via a first path;
• generating, by the first access controller in the first die, a first access signal according to the first control signal to access a non-volatile memory via a second path;
• generating, by a second processor in the second die, a second control signal to a second access controller of the second die via a third path;
• generating, by the second access controller in the second die, a second access signal according to the second control signal to access the non-volatile memory via a fourth path;
• generating, by an arbiter, an arbitration signal according to the first and the second control signals;
• and
• controlling the first, the second, the third, and the fourth paths according to the arbitration signal;
• wherein the first die having a first power and a first operational clock and the second die having a second power and a second operational clock are independently operation.

A method of operating a multi-die system in a chip, the multi-die system comprising a first die and a second die, the first die comprising an arbiter coupled to the second die, the method comprising:

• the arbiter granting access for the first die to access a non-volatile memory by default;
• the first die accessing the non-volatile memory;
• after an access of the first die, a request signal being de-asserted for one cycle for the arbiter to perform arbitration;
• and
• the arbiter granting access for the first die or the second die to access the non-volatile memory according to an arbitration result;
• wherein the first die and the second die are independent operations.