Block mode toggling using hybrid controllers

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a processor to cause the processor to:

• maintain, by the processor, a block switching metric for each block of memory in a storage system;
• determine, by the processor, whether a first block in a first pool should be transferred to a second pool according to a block switching metric which corresponds to the first block;
• in response to determining that the first block in the first pool should be transferred to the second pool according to the block switching metric which corresponds to the first block, erase, by the processor, the first block;
• transfer, by the processor, the first block from the first pool to a second ready-to-use (RTU) queue which corresponds to the second pool;
• erase, by the processor, a second block;
• and
• transfer, by the processor, the second block from the second pool to a first RTU queue which corresponds to the first pool,
• wherein the blocks in the first pool are configured in single-level cell (SLC) mode,
• wherein the blocks in the second pool are configured in multi-bit-per-cell mode.

A system, comprising:

• a plurality of non-volatile random access memory (NVRAM) blocks configured to store data;
• and
• a processor and logic integrated with and/or executable by the processor, the logic being configured to:
• maintain, by the processor, a block switching metric for each block of memory in a storage system;
• determine, by the processor, whether a first block in a first pool should be transferred to a second pool according to a block switching metric which corresponds to the first block;
• in response to determining that the first block in the first pool should be transferred to the second pool according to the block switching metric which corresponds to the first block, erase, by the processor, the first block;
• transfer, by the processor, the erased first block from the first pool to a second ready-to-use (RTU) queue which corresponds to the second pool;
• erase, by the processor, a second block in the second pool;
• and
• transfer, by the processor, the erased second block from the second pool to a first RTU queue which corresponds to the first pool,
• wherein the blocks in the first pool are configured in single-level cell (SLC) mode,
• wherein the blocks in the second pool are configured in multi-bit-per-cell mode.