# US 2020/0404752 A1 · Dynamic driver voltage headroom adjustment

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- Number: US 2020/0404752 A1
- Document ID: US20200404752A1
- Status: Published application
- Kind: A1
- Application number: 16/690,778
- Filed: 2019-11-21
- Published: 2020-12-24
- Earliest claimed: 2019-06-21
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Jiana LOU
- Web page: https://patentgrep.com/patent/US20200404752A1

## CPC

- H05B 45/10: Controlling the intensity of the light
- H03M 1/68: with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
- H03M 1/745: {with weighted currents}
- H05B 45/345: Current stabilisation; Maintaining constant current
- H05B 45/37: Converter circuits
- H05B 45/46: having LEDs disposed in parallel lines
- H05B: ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Aspects of the disclosure provide for a circuit including a binary-weighted DAC, a first transistor, a second transistor, a switch, a first current mirror, a second current mirror. The binary-weighted DAC is coupled between a first node and a second node and configured to receive a plurality of bits of a digital control signal. The first transistor has a source coupled to the first node, a drain coupled to a third node, and a gate coupled to a fourth node. The second transistor has a source coupled to the first node, a drain coupled to the third node, and a gate. The switch is coupled between the gate of the second transistor and the fourth node and configured to receive a partition control signal. The first current mirror is coupled to the third node and the second node. The second current mirror is coupled to the first current mirror.

## Claims

### Claim 1

A circuit, comprising:
a digital-to-analog converter (DAC) and configured to receive bits of a first control signal, the DAC comprising a first terminal and a second terminal;
a first transistor comprising:
a source terminal coupled to the first terminal of the DAC;
a drain terminal; and
a gate terminal;
a second transistor comprising:
a source terminal coupled to the first terminal of the DAC;
a drain terminal coupled to the drain terminal of the first transistor; and
a gate terminal;
a switch coupled between the gate terminal of the second transistor and the gate terminal of the first transistor, the switch configured to receive a second control signal;
a first current mirror coupled to the drain terminal of the first transistor and to the second terminal of the DAC;
a second current mirror coupled to the first current mirror; and
a third transistor comprising:
a source terminal coupled to the first terminal of the DAC;
a drain terminal coupled to the second terminal of the DAC; and
a gate terminal coupled to the gate terminal of the first transistor.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the DAC comprises:
transistors each comprising a source terminal coupled to the first terminal of the DAC, a drain terminal coupled to the second terminal of the DAC, and a gate terminal; and
switches, wherein each of the switches is coupled between a gate terminal of one of the transistors and the gate terminal of the first transistor, and wherein each of the switches is configured to receive and be controlled by one bit of bits of the first control signal,
wherein a number of the transistors and a number of the switches corresponds to a number of bits of the first control signal.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein the first current mirror comprises:
a fourth transistor comprising a source terminal coupled to the drain terminal of the first transistor, a drain terminal, and a gate terminal; and
a fifth transistor comprising a source terminal coupled to the second terminal of the DAC, a drain terminal coupled to the gate terminal of the fourth transistor, and a gate terminal coupled to the gate terminal of the fourth transistor.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the second current mirror comprises:
a sixth transistor comprising a source terminal coupled to a ground terminal, a drain terminal coupled to the drain terminal of the fourth transistor, and a gate terminal coupled to the drain terminal of the fourth transistor; and
a seventh transistor comprising a source terminal coupled to the ground terminal, a drain terminal coupled to the gate terminal of the fourth transistor, and a gate terminal coupled to the drain terminal of the fourth transistor.

### Claim 5 (depends on 4)

The circuit of claim 4, further comprising:
an eighth transistor comprising a source terminal coupled to the ground terminal, a drain terminal, and a gate terminal coupled to the drain terminal of the fourth transistor;
a buffer circuit comprising an input terminal coupled to the drain terminal of the eighth transistor and an output coupled to the gate terminal of the first transistor; and
a current source coupled between the first terminal of the DAC and the drain terminal of the eight transistor.

### Claim 6 (depends on 1)

The circuit of claim 1, further comprising a processing element configured to:
receive a brightness code;
generate the first control signal by mapping the brightness code to a first value range or a second value range based on a value of the brightness code; and
generate the second control signal based on the value of the brightness code, wherein the processing element comprises a first output and multiple second outputs, wherein the first output is coupled to the switch to provide the second control signal to the switch, and wherein the multiple second outputs are coupled to the DAC to provide the digital control signal to the DAC.

### Claim 7 (depends on 6)

The circuit of claim 6, wherein the processing element generates the digital control signal by:
performing a direct mapping from the brightness code to the first control signal in the first value range while the brightness code has a value in the first value range; and
performing an arithmetic left shift on the brightness code and complementing a least significant bit of the result of the arithmetic left shift while the brightness code has a value not in the first value range.

### Claim 8 (depends on 6)

The circuit of claim 6, wherein the processing element generates the second control signal having a value of 1 while the brightness code has a value in the first value range, and wherein the processing element generates the second control signal having a value of 2 while the brightness code has a value not in the first value range.

### Claim 9 (depends on 1)

The circuit of claim 1, further comprising:
a power source;
a power regulator comprising an input coupled to the power source and an output coupled to the first terminal of the DAC; and
a light-emitting diode coupled between the second terminal of the DAC and a ground terminal.

### Claim 10

A circuit, comprising:
a processing element configured to:
receive a digital input signal;
partition the digital input signal to generate a control signal, comprising:
while the digital input signal has a value in a first value range, mapping the digital input signal to a first value range; and
while the digital input signal has a value in a second value range, mapping the digital input signal to a second value range; and
generate a partition control signal in accordance with the digital input signal; and
a driver configured to drive a light-emitting diode by:
receiving the control signal from the processing element;
controlling a digital-to-analog converter (DAC) to generate a current for the light-emitting diode, responsive to the digital input signal and a reference current, with a first voltage headroom (VHR) value responsive to the partition control signal while the digital input signal has the value in the first value range; and
controlling the DAC to generate the current to the light-emitting diode with a second VHR value responsive to the partition control signal while the digital input signal has the value the second value range.

### Claim 11 (depends on 10)

The circuit of claim 10, wherein the driver comprises:
the DAC comprising a first terminal and a second terminal, and the DAC configured to receive the control signal from the processing element;
a first transistor comprising a source terminal coupled to the first terminal of the DAC, a drain terminal, and a gate terminal;
a second transistor comprising a source terminal coupled to the first terminal of the DAC, a drain terminal coupled to the drain terminal of the first transistor, and a gate terminal;
a switch coupled between the gate terminal of the second transistor and the gate terminal of the first transistor, the switch configured to receive the partition control signal;
a first current mirror coupled to the drain terminal of the first transistor and the second terminal of the DAC;
a second current mirror coupled to the first current mirror; and
a third transistor comprising a source terminal coupled to the first terminal of the DAC, a drain terminal coupled to the second terminal of the DAC, and a gate terminal coupled to the gate terminal of the first transistor.

### Claim 12 (depends on 11)

The circuit of claim 11, wherein the DAC comprises:
transistors each comprising a source terminal coupled to the first terminal of the DAC, a drain terminal coupled to the second terminal of the DAC, and a gate terminal; and
switches, wherein each of the switches is coupled between a gate terminal of one of the transistors and the gate terminal of the first transistor, and wherein each of the switches is configured to receive and be controlled by one bit of the control signal,
wherein a number of the transistors and a number of the switches corresponds to a number of bits of the control signal.

### Claim 13 (depends on 11)

The circuit of claim 11, wherein the first current mirror comprises:
a fourth transistor comprising a source terminal coupled to the drain terminal of the first transistor, a drain terminal, and a gate terminal; and
a fifth transistor comprising a source terminal coupled to the second terminal of the DAC, a drain terminal coupled to the drain terminal of the fourth transistor, and a gate terminal coupled to the gate terminal of the fourth transistor, and wherein the second current mirror comprises:
a sixth transistor comprising a source terminal coupled to a ground terminal, a drain terminal coupled to the drain terminal of the fourth transistor, and a gate terminal coupled to the drain terminal of the fourth transistor; and
a seventh transistor comprising a source terminal coupled to the ground terminal, a drain terminal coupled to the gate terminal of the fourth transistor, and a gate terminal coupled to the drain terminal of the fourth transistor.

### Claim 14 (depends on 13)

The circuit of claim 13, wherein the driver further comprises:
an eighth transistor comprising a source terminal coupled to the ground terminal, a drain terminal, and a gate terminal coupled to the drain terminal of the fourth transistor;
a buffer circuit comprising an input coupled to the drain terminal of the eighth transistor and an output coupled to the gate terminal of the first transistor; and
a current source coupled between the first terminal of the DAC and the drain terminal of the eighth transistor.

### Claim 15 (depends on 11)

The circuit of claim 11, further comprising:
a power source;
a power regulator comprising an input coupled to the power source and an output coupled to the first terminal of the DAC; and
a light-emitting diode coupled between the second terminal of the DAC and a ground terminal.

### Claim 16 (depends on 11)

The circuit of claim 11, wherein the first VHR is greater than the second VHR, and wherein the second VHR is reduced without modifying the reference current.

### Claim 17

A system, comprising:
a power regulator comprising an input adapted to be coupled to a power source, and the power regulator comprising an output coupled to a first node;
a processing element configured to generate a digital control signal and a partition control signal according to a brightness code;
a driver, comprising:
a digital-to-analog converter (DAC) comprising a first terminal coupled to the output of power regulator, and a second terminal, and the DAC configured to receive the digital control signal from the processing element;
a first transistor comprising a source terminal coupled to the first terminal of the DAC, a drain terminal, and a gate terminal;
a second transistor comprising a source terminal coupled to the first terminal of the DAC, a drain terminal coupled to the drain terminal of the first transistor, and a gate terminal;
a switch coupled between the gate terminal of the second transistor and the gate terminal of the first transistor, the switch configured to receive the partition control signal from the processing element;
a first current mirror coupled to the drain terminal of the first transistor and to the second terminal of the DAC;
a second current mirror coupled to the first current mirror; and
a third transistor comprising a source terminal coupled to the first terminal of the DAC, a drain terminal coupled to the second terminal of the DAC, and a gate terminal coupled to the gate terminal of the first transistor; and
a light-emitting diode coupled between the second terminal of the DAC and a ground terminal.

### Claim 18 (depends on 17)

The system of claim 17, wherein the processing element is further configured to:
receive the brightness code;
generate the digital control signal by mapping the brightness code to a first value range or to a second value range based on the brightness code, wherein the brightness code is mapped to a first value range while the brightness code has a value in the first value range and the brightness code is mapped to a second value range while the brightness code has a value in the second value range; and
generate the partition control signal based on the brightness code, wherein a first output of the processing element is coupled to the switch to provide the partition control signal to the switch, and wherein multiple outputs of the processing element are coupled to the DAC to provide the digital control signal to the DAC.

### Claim 19 (depends on 17)

The system of claim 17, wherein the partition control signal instructs the driver to drive the light-emitting diode with an current responsive to the digital control signal and a voltage headroom responsive to the partition control signal, and wherein the voltage headroom is greater while brightness code is in the first value range than while the brightness code is in the second value range.

### Claim 20 (depends on 17)

The system of claim 17, wherein the DAC comprises:
transistors each having a source terminal coupled to the first terminal of the DAC, a drain terminal coupled to the second terminal of the DAC, and a gate terminal; and
switches, wherein each of the switches is coupled between a gate terminal of one of the transistors and the gate terminal of the first transistor, and wherein each of the switches is configured to receive and be controlled by one bit of bits of the digital control signal,
wherein a number of the transistors and a number of the switches corresponds to a number of bits of the digital control signal.

### Claim 21 (depends on 20)

The system of claim 20, wherein the first current mirror comprises:
a fourth transistor comprising a source terminal coupled to the drain terminal of the first transistor, a drain terminal, and a gate terminal; and
a fifth transistor comprising a source terminal coupled to the second terminal of the DAC, a drain terminal coupled to the gate terminal of the fourth transistor, and a gate terminal coupled to the gate terminal of the fourth transistor, and wherein the second current mirror comprises:
a sixth transistor comprising a source terminal coupled to a ground node terminal, a drain terminal coupled to the drain terminal of the fourth transistor, and a gate terminal coupled to the drain terminal of the fourth transistor; and
a seventh transistor comprising a source terminal coupled to the ground terminal, a drain terminal coupled to the gate terminal of the fourth transistor, and a gate terminal coupled to the drain terminal of the fourth transistor.

### Claim 22 (depends on 21)

The system of claim 21, further comprising:
an eighth transistor comprising a source terminal coupled to the ground terminal, a drain terminal, and a gate terminal coupled to the drain terminal of the fourth transistor;
a buffer circuit comprising an input coupled to the drain terminal of the eighth transistor and an output coupled to the gate terminal of the first transistor; and
a current source coupled between the first terminal of the DAC and the drain terminal of the eighth transistor.