# US 2020/0404199 A1 · Pixel Sensor Cell for CMOS Image Sensors with Enhanced Conversion Gain at High Dynamic Range Capability > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0404199 A1 - Document ID: US20200404199A1 - Status: Published application - Kind: A1 - Application number: 16/765,036 - Filed: 2017-11-20 - Published: 2020-12-24 - Earliest claimed: 2017-11-20 - Assignees: Ecole Polytechnique Federale De Lausanne Epfl-Tto - Applicants: Ecole Polytechnique FéDéRale De Lausanne Epfl-Tto - Inventors: Assim Boukhayma - Web page: https://patentgrep.com/patent/US20200404199A1 ## CPC - H04N 25/575: {with a response composed of multiple slopes} - H04N 25/59: by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance - H04N 25/76: Addressed sensors, e.g. MOS or CMOS sensors - H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components - H04N 25/771: comprising storage means other than floating diffusion - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract The present invention relates to a pixel sensor cell (1) for a CMOS sensor device comprising: —a photodiode (11) for generating photoelectrons; —a first transfer transistor (12) coupling the photodiode (11) with an intermediate node (IN) and configured to be controlled by a first control signal (TX1); —a gain reducing capacitance (CHD) applied on the intermediate node (IN); —a second transfer transistor (14) coupling the intermediate node (IN) with a sense node (SN) and configured to be controlled by a second control signal (TX2); —an output buffer (15) coupled with the sense node (SN) and configured to amplify a potential on the sense node (SN). ## Claims ### Claim 1 A pixel sensor cell for a CMOS sensor device comprising: a photodiode for generating photoelectrons; a first transfer transistor coupling the photodiode with an intermediate node and configured to be controlled by a first control signal; a gain reducing capacitance applied on the intermediate node; a second transfer transistor coupling the intermediate node with a sense node and configured to be controlled by a second control signal; an output buffer coupled with the sense node and configured to amplify a potential on the sense node. ### Claim 2 (depends on 1) The pixel sensor cell according to claim 1, wherein a reset transistor is provided which is configured to receive a reset signal and to selectively couple a supplied reset voltage to the intermediate node. ### Claim 3 (depends on 1) The pixel sensor cell according to claim 1, wherein the intermediate node is provided with a gain reducing capacitance which particularly is formed as a p+n junction. ### Claim 4 (depends on 1) The pixel sensor cell according to claim 1, wherein a control unit is provided to control operation of the pixel sensor cell by timely providing the first and second control signal. ### Claim 5 (depends on 1) The pixel sensor cell according to claim 1, wherein the photodiode is formed as a pinned photodiode. ### Claim 6 (depends on 1) The pixel sensor cell according to claim 1, wherein the transistors are formed as MOSFET transistors. ### Claim 7 (depends on 1) The pixel sensor cell according to claim 1, wherein the output buffer is formed with a selectable source follower. ### Claim 8 A method for operating a pixel sensor cell, comprising: accumulating photoelectrons in a photodiode during a predetermined integration time, a first transfer transistor coupling the photodiode with an intermediate node and configured to be controlled by a first control signal; in a first phase, coupling an intermediate node with a sense node by means of a second transfer transistor and providing a charge threshold for accumulated photoelectrons so that only excess photoelectrons are allowed to pass to the intermediate node, wherein the potential generated by the excess photoelectrons is read out as an HDS sampling output signal; in a second phase, controlling the second transfer transistor to set a threshold of the second transfer transistor to a potential where the second transfer transistor isolates the intermediate node and the sense node and which is substantially equal or higher than the potential of the intermediate node, coupling the intermediate node with the sense node and reading out the potential on the sense node as an LLS sampling output signal. ### Claim 9 (depends on 8) The method according to claim 8, wherein a cell output is determined depending on the LLS sampling output signal and the HDS sampling output signal. ### Claim 10 (depends on 9) The method according to claim 9, wherein after the first phase a first reset potential is loaded on the sense node and a second reset potential which is in a range between a pin voltage pin of the photodiode and the first reset potential. ### Claim 11 (depends on 10) The method according to claim 10, wherein after resetting the sense node and after the threshold of the second transfer transistor has been set to a potential where the second transfer transistor isolates the intermediate node and the sense node and which is substantially equal or higher than the potential of the intermediate node, reading out a reference sampling output signal, wherein the cell output is further determined depending on the reference sampling output signal. ### Claim 12 (depends on 10) The method according to claim 10, wherein after reading out the potential on the sense node as a LLS sampling output signal, the second transfer transistor is controlled to electrically merge the intermediate node and the sense node, reset the intermediate and sense nodes onto the first reset potential. ### Claim 13 A CMOS image sensor including an array of multiple pixel sensor cells, wherein each pixel cell comprises: a photodiode for generating photoelectrons; a first transfer transistor coupling the photodiode with an intermediate node and configured to be controlled by a first control signal; a gain reducing capacitance applied on the intermediate node; a second transfer transistor coupling the intermediate node with a sense node and configured to be controlled by a second control signal; an output buffer coupled with the sense node and configured to amplify a potential on the sense node. ### Claim 14 (depends on 13) The sensor of according to claim 13, wherein the intermediate node is provided with a gain reducing capacitance which particularly is formed as a p+n junction. ### Claim 15 (depends on 13) The sensor of according to claim 13, wherein a control unit is provided to control operation of the pixel sensor cell by timely providing the first and second control signal. ### Claim 16 (depends on 13) The sensor of according to claim 13, wherein the photodiode is formed as a pinned photodiode. ### Claim 17 (depends on 13) The sensor of according to claim 13, wherein the transistors are formed as MOSFET transistors. ### Claim 18 (depends on 13) The sensor of according to claim 13, wherein the output buffer is formed with a selectable source follower.