# US 2020/0403630 A1 · Self-trim of integrated circuit

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- Number: US 2020/0403630 A1
- Document ID: US20200403630A1
- Status: Published application
- Kind: A1
- Application number: 16/446,348
- Filed: 2019-06-19
- Published: 2020-12-24
- Earliest claimed: 2019-06-19
- Applicants: Texas Instruments Incorporated
- Inventors: Vadim Valerievich IVANOV; Srinivas Kumar PULIJALA; Munaf Hussain SHAIK
- Web page: https://patentgrep.com/patent/US20200403630A1

## CPC

- H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14)
- H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)}
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03K 5/24: the characteristic being amplitude
- H03M 1/66: Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence)
- H03F 2200/129: there being a feedback over the complete amplifier
- H03F 2203/45048: Calibrating and standardising a dif amp
- H03F 2203/45116: Feedback coupled to the input of the differential amplifier
- H03M 1/46: with digital/analogue converter for supplying reference values to converter
- H03M 1/765: {using a single level of switches which are controlled by unary decoded digital signals}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03F: AMPLIFIERS
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An integrated circuit (IC) includes a current source device configured to generate a bias current. The IC also includes a comparator, a circuit, a memory, and a digital-to-analog circuit (DAC). The comparator has a first input, a second input, and a comparator output. The first input receives a reference voltage, and the second input receives a voltage indicative of a bias current through the IC. The circuit is coupled to the comparator output. The circuit iteratively generates a final trim code based on an output signal from the comparator. The memory stores the final trim code. The DAC controls a level of the bias current through the current source device based on the final trim code.

## Claims

### Claim 1

An integrated circuit, comprising:
an electrical circuit having a bias terminal configured to receive a bias current from a current generator;
a comparator having a first input, a second input, and a comparator output, the first input coupled to a bandgap reference source and the second input coupled to receive a voltage indicative of the bias current;
a successive approximation register (SAR) circuit having an input coupled to the comparator output, the SAR circuit configured to provide at a SAR output a final trim code based on an output signal from the comparator;
a memory coupled to the SAR output, the memory configured to store the final trim code;
a digital-to-analog circuit (DAC) having an input coupled to the SAR output and having an output; and
a bias generator circuit having an input coupled to the output of the DAC and an output coupled to the electrical circuit, and configured to provide a control signal at an output of the bias generator to control the bias current.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein prior to providing the final trim code, the SAR circuit iteratively provides at least one interim trim code, and wherein, in each iteration, the SAR circuit is configured to change a logic state of one bit within a respective interim trim code.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein, within each iteration, the SAR circuit is configured to change the logic state of the most significant bit (MSB) first.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the final trim code is a multibit value, and wherein the SAR circuit is configured to:
initialize a trim code to an initial value;
change a logic state of the most significant bit of the initial value from a first logic state to a second logic state;
determine a logic state of the comparator's output signal; and
change the logic state of the most significant bit back to the first logic state responsive to a change in the logic state of the comparator's output signal.

### Claim 5 (depends on 4)

The integrated circuit of claim 4, wherein the SAR circuit is configured to:
iteratively change a logic state of each successive bit of the trim code from the most significant bit to the least significant bit to generate the final trim code; one respective bit of the trim code changing state within each iteration and
with each iteration, responsive to the comparator's output signal changing state, change back the logic state of the respective bit.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, including an amplifier having a control terminal coupled to the bias generator output, and wherein the DAC includes a series chain of resistors.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, further including a first transistor having a current terminal coupled to the series chain of resistors.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, including further comprising a second transistor, and wherein:
the first transistor having a first control input and a current terminal;
the second transistor having a second control input coupled to the first control input and to an output of the amplifier;
and
the amplifier includes a first amplifier input configured to receive a reference voltage and a second amplifier input coupled to the series chain of resistors and the current terminal of the first transistor.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, wherein the electrical circuit includes an operational amplifier.

### Claim 10

A system, comprising:
a printed circuit board (PCB);
a voltage supply node on the PCB;
a device coupled to the PCB and to the voltage supply node, the device including:
an electrical circuit having a bias terminal configured to receive a bias current from a current generator;
a comparator having a first input, a second input, and a comparator output, the first input coupled to a bandgap reference source and the second input coupled to receive a voltage indicative of the bias current;
a successive approximation register (SAR) circuit having an input coupled to the comparator output, the SAR circuit configured to provide at a SAR output a final trim code based on an output signal from the comparator;
a memory coupled to the SAR output, the memory configured to store the final trim code;
a digital-to-analog circuit (DAC) having an input coupled to the SAR output, and having an output; and
a bias generator circuit having an input coupled to the output of the DAC and an output coupled to the electrical circuit, and configured to provide a control signal at an output of the bias generator to control the bias current.

### Claim 11 (depends on 10)

The system of claim 10, wherein:
prior to providing the final trim code, the SAR circuit iteratively provides at least one interim trim code;
in each iteration, the SAR circuit is configured to change a logic state of one bit within a respective interim trim code; and
in each iteration, the DAC is configured to change the level of the bias current through the electrical circuit.

### Claim 12 (depends on 10)

The system of claim 10, wherein the final trim code is a multibit value, and wherein the SAR circuit is configured to:
initialize a trim code to an initial value;
change a logic state of the most significant bit of the initial value from a first logic state to a second logic state;
determine a logic state of the comparator's output signal; and
change the logic state of the most significant bit back to the first logic state responsive to a change in the logic state of the comparator's output signal.

### Claim 13 (depends on 12)

The system of claim 12, wherein the SAR circuit is configured to:
iteratively change a logic state of each successive bit of the trim code from the most significant bit to the least significant bit to generate the final trim code; one respective bit of the trim code changing state within each iteration and
with each iteration, responsive to the comparator's output signal changing state, change back the logic state of the respective bit.

### Claim 14 (depends on 10)

The system of claim 10, including an amplifier having first and second amplifier inputs and an output, and wherein the DAC comprises a series chain of resistors and a plurality of switches, each switch being coupled in parallel with a respective one of the resistors, and a first resistor in the series chain being coupled to the first amplifier input.

### Claim 15 (depends on 14)

The system of claim 14, further including a first transistor having a first control input and having a current terminal coupled to the first resistor in the series chain of resistors, wherein when a current flows through the transistor, the current also flows through the chain of resistors.

### Claim 16 (depends on 15)

The system of claim 15, further including a second transistor wherein:
the second transistor includes a second control input coupled to the first control input and to the output of the amplifier;
and
the second input of the amplifier is configured to receive a reference voltage.

### Claim 17 (depends on 10)

The system of claim 10, further including a resistor mounted on the PCB and coupled between the voltage supply node and the device.

### Claim 18

A method, comprising:
initializing a multi-bit trim code; and
iteratively determining a final trim code, each iteration including:
changing a bit of the multi-bit trim code from a first logic state to a second logic state;
adjusting a bias current to produce an adjusted bias current; and
responsive to the adjusted bias current changing by more than a threshold amount, changing the bit back to the first logic state.

### Claim 19 (depends on 18)

The method of claim 18, wherein iteratively determining the final trim code comprises changing each bit of the multi-bit trim code starting with the most significant bit and ending with the least significant bit of the multi-bit trim code.

### Claim 20 (depends on 18)

The method of claim 18, further including storing the trim code in a non-volatile memory.