# US 2020/0403146 A1 · Memory cell with top electrode via

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- Number: US 2020/0403146 A1
- Document ID: US20200403146A1
- Status: Published application
- Kind: A1
- Application number: 17/009,887
- Filed: 2020-09-02
- Published: 2020-12-24
- Earliest claimed: 2018-07-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ming-Che Ku; Harry-Hak-Lay Chuang; Hung Cho Wang; Tsun Chung Tu; Jiunyu Tsai; Sheng-Huang Huang
- Web page: https://patentgrep.com/patent/US20200403146A1

## CPC

- H10N 50/80: Constructional details
- H01F 10/3254: {the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]}
- H01F 41/34: in patterns, e.g. by lithography
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- H10W 20/085: {involving intermediate temporary filling with material}
- H10W 20/087: {involving multiple stacked pre-patterned masks}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A top electrode via couples the top electrode to an upper interconnect wire. A first line is tangent to a first outermost sidewall of the top electrode via and a second line is tangent to an opposing second outermost sidewall of the top electrode via. The first line is oriented at a first angle with respect to a horizontal plane that is parallel to an upper surface of the substrate and the second line is oriented at a second angle with respect to the horizontal plane. The second angle is less than the first angle.

## Claims

### Claim 1

An integrated chip, comprising:
a memory device surrounded by a dielectric structure disposed over a substrate, wherein the memory device comprises a data storage structure disposed between a bottom electrode and a top electrode;
a top electrode via coupling the top electrode to an upper interconnect wire;
wherein a first line is tangent to a first outermost sidewall of the top electrode via and a second line is tangent to an opposing second outermost sidewall of the top electrode via; and
wherein the first line is oriented at a first angle with respect to a horizontal plane that is parallel to an upper surface of the substrate and the second line is oriented at a second angle with respect to the horizontal plane, the second angle less than the first angle.

### Claim 2 (depends on 1)

The integrated chip of claim 1, wherein the second outermost sidewall is a curved sidewall.

### Claim 3 (depends on 1)

The integrated chip of claim 1,
wherein the top electrode via has a bottom surface; and
wherein the top electrode via laterally extends a first distance past a first edge of the bottom surface and a second distance past an opposing second edge of the bottom surface, the first distance being larger than the second distance.

### Claim 4 (depends on 1)

The integrated chip of claim 1, wherein the top electrode via has a bottom surface that is centered along a vertical line, the vertical line offset from a center of the top electrode via by a non-zero distance.

### Claim 5 (depends on 1)

The integrated chip of claim 1,
wherein a bottom surface of the top electrode via extends for a first distance in a first direction and for a second distance in a second direction, the second distance larger than the first distance; and
wherein the first direction and the second direction are parallel to the upper surface of the substrate.

### Claim 6 (depends on 1)

The integrated chip of claim 1, wherein a top of the top electrode via is off centered from a bottom of the top electrode via.

### Claim 7 (depends on 1)

The integrated chip of claim 1, wherein the top electrode via has a first width extending from the first outermost sidewall to the second outermost sidewall, the first width being less than or equal to approximately 25 nm.

### Claim 8 (depends on 1)

The integrated chip of claim 1, further comprising:
a second via disposed within the dielectric structure and laterally separated from the top electrode via, wherein the top electrode via has a first width and the second via has a second width that is larger than the first width.

### Claim 9 (depends on 8)

The integrated chip of claim 8, wherein the top electrode via has a first height and the second via has a second height that is larger than the first height.

### Claim 10

An integrated chip, comprising:
a memory device laterally surrounded by an inter-level dielectric (ILD) layer disposed over a substrate, wherein the memory device comprises a data storage structure disposed between a bottom electrode and a top electrode; and
a top electrode via coupling the top electrode to an upper interconnect wire, wherein a bottom surface of the top electrode via has an oval shape.

### Claim 11 (depends on 10)

The integrated chip of claim 10, further comprising:
a second via laterally separated from the top electrode via by the ILD layer, wherein the top electrode via has a first width and the second via has a second width that is larger than the first width.

### Claim 12 (depends on 10)

The integrated chip of claim 10, further comprising:
a second via laterally separated from the top electrode via by the ILD layer, wherein the second via has a different shape than the top electrode via as viewed along a top-view.

### Claim 13 (depends on 10)

The integrated chip of claim 10, wherein the top electrode via extends below a top of the top electrode.

### Claim 14 (depends on 10)

The integrated chip of claim 10, wherein a top of the top electrode via is at least twice as wide as a bottom of the top electrode via.

### Claim 15

An integrated chip, comprising:
a memory device laterally surrounded by an inter-level dielectric (ILD) material disposed over a substrate, wherein the memory device comprises a data storage structure disposed between a bottom electrode and a top electrode; and
a top electrode via coupling the top electrode to an upper interconnect wire, wherein the top electrode via is asymmetric with respect to a line bisecting the top electrode via as viewed along a cross-sectional view of the top electrode via.

### Claim 16 (depends on 15)

The integrated chip of claim 15,
wherein the top electrode via has a bottom surface; and
wherein the top electrode via laterally extends past the bottom surface in a first direction for a first distance and the top electrode via laterally extends past the bottom surface in an opposing second direction for a second distance that is larger than the first distance.

### Claim 17 (depends on 15)

The integrated chip of claim 15, wherein a side of the top electrode via is defined by a slope that decreases as a distance from the top electrode increases.

### Claim 18 (depends on 15)

The integrated chip of claim 15, wherein a first side of the top electrode via has a first slope and an opposing second side of the top electrode via has a second slope that is greater than the first slope.

### Claim 19 (depends on 15)

The integrated chip of claim 15, wherein a bottom of the top electrode via is off centered from a top of the top electrode via.

### Claim 20 (depends on 15)

The integrated chip of claim 15, further comprising:
a second via laterally separated from the top electrode via by the ILD material, wherein a bottom surface of the second via has a larger width than a bottom surface of the top electrode via.