# US 2020/0403101 A1 · Semiconductor device and method for manufacturing semiconductor device

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- Number: US 2020/0403101 A1
- Document ID: US20200403101A1
- Status: Published application
- Kind: A1
- Application number: 16/968,796
- Filed: 2019-02-19
- Published: 2020-12-24
- Earliest claimed: 2018-02-28
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei YAMAZAKI; Haruyuki BABA; Shiori MURAYAMA
- Web page: https://patentgrep.com/patent/US20200403101A1

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/80: characterised by the materials
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 41/70: the floating gate being an electrode shared by two or more components
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device with high on-state current is provided. The semiconductor device includes a transistor. The transistor includes a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide; a first conductor and a second conductor over the second oxide; a second insulator; a third conductor; a fourth insulator over the first conductor and the second conductor; and a third insulator over the fourth insulator. An opening reaching the second oxide is provided in the third insulator and the fourth insulator. The third oxide is positioned to cover an inner wall of the opening. The second insulator is positioned to cover the inner wall of the opening with the third oxide therebetween. The third conductor is positioned to fill the opening with the third oxide and the second insulator therebetween. In the channel length direction of the transistor, an angle formed by a bottom surface of the first insulator and a side surface of the first conductor facing the second conductor is smaller than 90°.

## Claims

### Claim 1

A semiconductor device comprising a transistor,
wherein the transistor comprises a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide over the second oxide; a first conductor and a second conductor over the second oxide; a second insulator over the third oxide; a third conductor over the second insulator; a fourth insulator over the first conductor and the second conductor; and a third insulator over the fourth insulator,
wherein an opening reaching the second oxide is provided in the third insulator and the fourth insulator,
wherein the third oxide is positioned to cover an inner wall of the opening,
wherein the second insulator is positioned to cover the inner wall of the opening with the third oxide therebetween,
wherein the third conductor is positioned to fill the opening with the third oxide and the second insulator therebetween, and
wherein a first angle formed by a plane parallel to a bottom surface of the first insulator and a side surface of the first conductor, the side surface facing the second conductor, is smaller than 90° in a channel length direction of the transistor.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the fourth insulator comprises a region in contact with a side surface of the first conductor, a side surface of the second oxide, and a side surface of the first oxide, and
wherein a second angle formed by the plane parallel to the bottom surface of the first insulator and a plane parallel to a side end portion of the fourth insulator in the region, the side end portion facing the second conductor, is smaller than 90° in the channel length direction of the transistor.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the first angle and the second angle are the same angle.

### Claim 4

A semiconductor device comprising a transistor,
wherein the transistor comprises a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide over the second oxide; a first conductor and a second conductor over the second oxide; a second insulator over the third oxide; a third conductor over the second insulator; a fourth insulator over the first conductor and the second conductor; and a third insulator over the fourth insulator,
wherein an opening reaching the second oxide is provided in the third insulator and the fourth insulator,
wherein the third oxide is positioned to cover an inner wall of the opening,
wherein the second insulator is positioned to cover the inner wall of the opening with the third oxide therebetween,
wherein the third conductor is positioned to fill the opening with the third oxide and the second insulator therebetween,
wherein on the basis of a bottom surface of the first insulator, a level of a bottom surface of the third conductor in a region not overlapping with the second oxide is lower than a level of a bottom surface of the second oxide in a channel width direction of the transistor, and
wherein a length of the bottom surface of the third conductor in the region not overlapping with the second oxide is shorter than a length of the bottom surface of the third conductor in a region overlapping with the second oxide in a channel length direction of the transistor.

### Claim 5

A semiconductor device comprising a transistor,
wherein the transistor comprises a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide over the second oxide; a first conductor and a second conductor over the second oxide; a second insulator over the third oxide; a third conductor over the second insulator; a fourth insulator over the first conductor and the second conductor; and a third insulator over the fourth insulator,
wherein an opening reaching the second oxide is provided in the third insulator and the fourth insulator,
wherein the third oxide is positioned to cover an inner wall of the opening,
wherein the second insulator is positioned to cover the inner wall of the opening with the third oxide therebetween,
wherein the third conductor is positioned to fill the opening with the third oxide and the second insulator therebetween, and
wherein a side end portion of the fourth insulator has a curved shape when the transistor is seen from the above.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the fourth insulator comprises an oxide of aluminum.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1,
wherein the second oxide comprises In, an element M, and Zn, and
wherein the element M is Al, Ga, Y, or Sn.

### Claim 8 (depends on 4)

The semiconductor device according to claim 4, wherein the fourth insulator comprises an oxide of aluminum.

### Claim 9 (depends on 5)

The semiconductor device according to claim 5, wherein the fourth insulator comprises an oxide of aluminum.

### Claim 10 (depends on 4)

The semiconductor device according to claim 4,
wherein the second oxide comprises In, an element M, and Zn, and
wherein the element M is Al, Ga, Y, or Sn.

### Claim 11 (depends on 5)

The semiconductor device according to claim 5,
wherein the second oxide comprises In, an element M, and Zn, and
wherein the element M is Al, Ga, Y, or Sn.