# US 2020/0403097 A1 · Method of forming isolation dielectrics for stacked field effect transistors (fets)

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- Number: US 2020/0403097 A1
- Document ID: US20200403097A1
- Status: Published application
- Kind: A1
- Application number: 16/548,209
- Filed: 2019-08-22
- Published: 2020-12-24
- Earliest claimed: 2019-06-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Wei-E WANG; Mark RODDER; Vassilios GEROUSIS
- Web page: https://patentgrep.com/patent/US20200403097A1

## CPC

- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10P 90/1914: {using bonding}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a stacked field effect transistor (FET) circuit is provided. The method includes providing a first wafer and a second wafer, forming a first dielectric layer on a surface of the first wafer, forming a second dielectric layer on a surface of the second wafer, and bonding the first wafer to the second wafer at the first dielectric layer and the second dielectric layer.

## Claims

### Claim 1

A method of forming a stacked field effect transistor (FET) circuit, comprising:
providing a first wafer and a second wafer;
forming a first dielectric layer on a surface of the first wafer;
forming a second dielectric layer on a surface of the second wafer; and
bonding the first wafer to the second wafer at the first dielectric layer and the second dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising performing a low temperature epitaxial (EPI) growth on the first wafer and the second wafer.

### Claim 3 (depends on 1)

The method of claim 1, further comprising applying a de-bonding anneal with a chemical-mechanical polish (CMP) process after bonding the first wafer to the second layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the dielectric layer is at least one of Si3N4, SiCN, HfO2 or Al3O3.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second wafer is a handler silicon on insulator (SOI) wafer.

### Claim 6 (depends on 1)

The method of claim 1, wherein stacked FET circuit is a configuration of two FETs.

### Claim 7 (depends on 6)

The method of claim 6, wherein the configuration of two FETs comprises a top silicon channel and a bottom silicon channel.

### Claim 8 (depends on 6)

The method of claim 6, wherein the configuration of two FETs comprises a top silicon channel and a bottom Si/Ge channel.

### Claim 9 (depends on 6)

The method of claim 6, wherein the configuration of two FETs comprises a top Si/Ge channel and a bottom silicon channel.

### Claim 10 (depends on 1)

The method of claim 1, wherein a total thickness of the first dielectric layer and the second dielectric layer after bonding is about 5 nm to about 20 nm.

### Claim 11

A stacked field effect transistor (FET) circuit, comprising:
a first wafer including a first dielectric layer formed on a surface of the first wafer; and
a second wafer including a second dielectric layer formed on a surface of the second wafer,
wherein the first wafer and the second wafer are bonded at the first dielectric layer and the second dielectric layer.

### Claim 12 (depends on 11)

The circuit of claim 11, wherein a low temperature epitaxial (EPI) growth is performed on the first wafer and the second wafer.

### Claim 13 (depends on 11)

The circuit of claim 11, wherein a de-bonding anneal with a chemical-mechanical polish (CMP) process is applied after the first wafer is bonded to the second layer.

### Claim 14 (depends on 11)

The circuit of claim 11, wherein the dielectric layer is at least one of Si3N4, SiCN, HfO2 or Al3O3.

### Claim 15 (depends on 11)

The circuit of claim 11, wherein the second wafer is a handler silicon on insulator (SOI) wafer.

### Claim 16 (depends on 11)

The circuit of claim 11, wherein stacked FET circuit is a configuration of two FETs.

### Claim 17 (depends on 16)

The circuit of claim 16, wherein the configuration of two FETs comprises a top silicon channel and a bottom silicon channel.

### Claim 18 (depends on 16)

The circuit of claim 16, wherein the configuration of two FETs comprises a top silicon channel and a bottom Si/Ge channel.

### Claim 19 (depends on 16)

The circuit of claim 16, wherein the configuration of two FETs comprises a top Si/Ge channel and a bottom silicon channel.

### Claim 20 (depends on 11)

The circuit of claim 11, wherein a total thickness of the first dielectric layer and the second dielectric layer after bonding if about 5 nm to about 20 nm.

### Claim 21 (depends on 1)

The method of claim 1, wherein the dielectric layer comprises SiO2.

### Claim 22 (depends on 1)

The method of claim 1, wherein the first wafer or the second wafer comprise Ge.

### Claim 23 (depends on 6)

The method of claim 6, wherein the configuration of two FETs comprises a top channel and a bottom channel, and one or both of the top channel and the bottom channel is a Ge channel.

### Claim 24 (depends on 11)

The circuit of claim 11, wherein the dielectric layer comprises SiO2.

### Claim 25 (depends on 11)

The circuit of claim 11, wherein the first wafer or the second wafer comprise Ge.

### Claim 26 (depends on 16)

The circuit of claim 16, wherein the configuration of two FETs comprises a top channel and a bottom channel, and one or both of the top channel and the bottom channel is a Ge channel.