# US 2020/0403071 A1 · Method for testing a high voltage transistor with a field plate

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- Number: US 2020/0403071 A1
- Document ID: US20200403071A1
- Status: Published application
- Kind: A1
- Application number: 16/444,936
- Filed: 2019-06-18
- Published: 2020-12-24
- Earliest claimed: 2019-06-18
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Ramana Tadepalli; Chang Soo Suh
- Web page: https://patentgrep.com/patent/US20200403071A1

## CPC

- H10D 64/112: {comprising multiple field plate segments}
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- G01R 31/2601: {Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence)}
- G01R 31/2621: {for testing field effect transistors, i.e. FET's}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10W 20/031: {of conductive parts of the interconnections}
- H10W 20/43: Layouts of interconnections
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/50: Bond wires
- H10W 72/90: Bond pads, in general
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10D 62/80: characterised by the materials
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/111: {Field plates}
- H10W 72/072: {of bump connectors}
- H10W 72/07254: {changes in dispositions}
- H10W 72/075: {of bond wires}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/251: {Materials}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5453: {connecting between multiple bond pads on a chip, e.g. daisy chain}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/551: {Materials of bond wires}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

## Claims

### Claim 1

An apparatus, comprising:
a transistor formed on a semiconductor substrate, the transistor comprising:
a transistor gate and an extended drain between the transistor gate and a transistor drain contact;
a transistor source contact coupled to a source contact probe pad;
a first dielectric layer covering the semiconductor substrate and the transistor gate;
a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and
the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first dielectric layer comprises a first inter-metal dielectric layer/pre-metal dielectric layer dielectric stack.

### Claim 3 (depends on 2)

The apparatus of claim 2, the transistor further comprising:
a gate field plate over the pre-metal dielectric layer; and
the gate field plate capacitively coupled through the pre-metal dielectric layer to a second portion of the extended drain that is between the transistor gate and the first portion of the extended drain.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the gate field plate couples to the transistor gate in an opening through the pre-metal dielectric layer.

### Claim 5 (depends on 3)

The apparatus of claim 3, wherein the gate field plate is coupled to a gate field plate probe pad, and the transistor gate is coupled to a gate probe pad.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the transistor comprises a gallium nitride (GaN) transistor.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the transistor comprises a gallium oxide (Ga2O3) transistor.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the transistor comprises a silicon drain extended metal oxide semiconductor (DEMOS) transistor.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the source field plate of the transistor further comprises:
a first source field plate capacitively coupled through a first inter-metallic dielectric layer/pre-metal dielectric layer dielectric stack to the first portion of the extended drain adjacent to the transistor gate;
the first source field plate coupled to a first source field plate probe pad;
a second source field plate capacitively coupled through a second inter-metal dielectric layer/first inter-metal dielectric layer/pre-metal dielectric layer dielectric stack to a third portion of the extended drain between the first portion of the extended drain and the transistor drain contact; and
the second source field plate coupled to a second source field plate probe pad.

### Claim 10 (depends on 9)

The apparatus of claim 9, the transistor further comprising:
a gate field plate over the pre-metal dielectric layer, the gate field plate capacitively coupled to a second portion of the extended drain through the pre-metal dielectric layer, the second portion of the extended drain located between the gate and the first portion of the extended drain.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the gate field plate is coupled to the transistor gate in an opening through the pre-metal dielectric layer.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein the gate field plate is coupled to a gate field plate probe pad and the transistor gate is coupled to a gate probe pad that is spaced from and electrically isolated from the gate field probe pad.

### Claim 13

An apparatus, comprising:
a transistor formed on a semiconductor substrate having a transistor gate and an extended drain between the transistor gate and a transistor drain contact, the transistor further comprising:
a transistor source contact;
a pre-metal dielectric layer covering a portion of the semiconductor substrate and the transistor gate;
a gate field plate over the pre-metal dielectric layer and overlying a portion of the transistor gate and capacitively coupled through the pre-metal dielectric layer to a first portion of the extended drain adjacent to the transistor gate;
a first inter-metal dielectric layer covering the pre-metal dielectric layer and the gate field plate;
a source field plate over the first inter-metal dielectric layer;
the source field plate overlying an end of the gate field plate and overlying a second portion of the extended drain between the first portion of the extended drain and the transistor drain contact;
the source field plate capacitively coupled to the second portion of the extended drain through a dielectric stack of the first inter-metal dielectric layer/pre-metal dielectric layer;
the transistor source contact coupled to a transistor source probe pad; and
the source field plate coupled to a source field plate probe pad.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the source field plate of the transistor is a first source field plate and further comprising:
a second inter-metal dielectric layer covering the first inter-metal dielectric layer and the first source field plate; and
a second source field plate over the second inter-metal dielectric layer and coupled through a dielectric stack of the second inter-metal dielectric layer/first inter-metal dielectric layer/pre-metal dielectric layer to a third portion of the extended drain between the second portion of the extended drain and the drain contact.

### Claim 15

A method for testing, comprising:
grounding a source, a gate, a gate field plate, and a first source field plate of an extended drain transistor;
applying a voltage greater than ground to a drain probe pad of the extended drain transistor;
measuring a first leakage current between the drain probe pad and the first source field plate;
determining whether the first leakage current exceeds a first predetermined specification;
applying a voltage greater than ground on the first source field plate while keeping the source and the gate field plate grounded;
measuring a second leakage current between the drain probe pad of the extended drain transistor and the gate field plate; and
determining whether the second leakage current exceeds a second predetermined specification.

### Claim 16 (depends on 15)

The method of claim 15 further comprising:
grounding the source, the gate, the gate field plate, the first source field plate, and a second source field plate of the extended drain transistor;
measuring a third leakage current between the drain probe pad and the second source field plate; and
determining whether the third leakage current exceeds a third predetermined specification.

### Claim 17

A method, comprising:
applying a first voltage stress to a dielectric between a source field plate and an extended drain of a transistor while applying a second voltage different from the first voltage on a source of the transistor;
measuring a first leakage current between the source field plate and a drain of the transistor;
applying a second voltage stress to a dielectric between a gate field plate and the extended drain of the transistor;
measuring a second leakage current between the gate field plate and the drain;
coupling the source field plate to the source;
mounting a die including the transistor on a substrate;
coupling the transistor source to a first substrate lead;
coupling the transistor drain to a second substrate lead;
coupling a gate of the transistor to a third substrate lead; and
covering a portion of the transistor including the extended drain and the substrate with mold compound, forming a packaged extended drain transistor.

### Claim 18 (depends on 17)

The method of claim 17, wherein the source field plate is coupled to the source by coupling the source field plate and the source to a same substrate lead.

### Claim 19 (depends on 18)

The method of claim 18, wherein the source field plate is coupled to the source with a stitch bond.

### Claim 20 (depends on 18)

The method of claim 18, wherein the source field plate is coupled to the source with a bar of conductive material.

### Claim 21 (depends on 20)

The method of claim 20, wherein the bar of conductive material is deposited using ink jet deposition.

### Claim 22 (depends on 18)

The method of claim 18, wherein the source field plate is coupled to the source with a conductive portion of a redistribution layer.