# US 2020/0402991 A1 · Three-dimensional semiconductor memory devices and methods of fabricating the same

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- Number: US 2020/0402991 A1
- Document ID: US20200402991A1
- Status: Published application
- Kind: A1
- Application number: 17/011,051
- Filed: 2020-09-03
- Published: 2020-12-24
- Earliest claimed: 2017-11-20
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: EUNTAEK JUNG; Joongshik Shin
- Web page: https://patentgrep.com/patent/US20200402991A1

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/10: characterised by the top-view layout
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Three-dimensional semiconductor memory devices and methods of fabricating the same are provided. A memory device may include a semiconductor layer including first and second regions, first vertical structures on the first region and extending in a first direction perpendicular to a top surface of the semiconductor layer, and second vertical structures on the second region and extending in the first direction. The first vertical structure may include a vertical semiconductor pattern extending in the first direction and in contact with the semiconductor layer, and a first data storage pattern surrounding the vertical semiconductor pattern. The second vertical structure may include an insulation structure extending in the first direction and in contact with the semiconductor layer, and a second data storage pattern surrounding the insulation structure.

## Claims

### Claim 1

A three-dimensional semiconductor memory device, comprising:
a substrate including a first region and a second region;
an electrode structure including electrodes vertically stacked on the substrate;
a plurality of first vertical structures extending into the electrode structure on the first region; and
a plurality of second vertical structures extending into the electrode structure on the second region,
wherein each of the first vertical structures comprises:
a vertical semiconductor pattern extending into the electrode structure; and
a first data storage pattern between the vertical semiconductor pattern and the electrode structure,
wherein each of the second vertical structures comprises:
an insulation structure extending into the electrode structure; and
a second data storage pattern between the insulation structure and the electrode structure,
wherein each first vertical structure comprises a first width, and each second vertical structure comprises a second width greater than the first width,
wherein bottom surfaces of the insulation structures are lower than bottom surfaces of the vertical semiconductor patterns and bottom surfaces of the second data storage patterns,
wherein the first data storage pattern of one of the first vertical structures comprises a first thickness on a sidewall of the vertical semiconductor pattern of the one of the first vertical structures,
wherein the second data storage pattern of one of the second vertical structures comprises a second thickness on the sidewall of the insulation structure of the one of the second vertical structures, and
wherein the second thickness is substantially equal to or less than the first thickness.

### Claim 2 (depends on 1)

The device of claim 1, wherein each of the first and second vertical structures comprises a tunnel insulation layer, a charge storage layer, and a blocking insulation layer that are sequentially stacked.

### Claim 3 (depends on 1)

The device of claim 1, wherein a thickness of one of the vertical semiconductor patterns is less than half a width of one of the insulation structures.

### Claim 4 (depends on 1)

The device of claim 1, wherein at least one of the insulation structures directly contacts the substrate.

### Claim 5

A method of fabricating a three-dimensional semiconductor memory device, the method comprising:
forming a mold structure on a substrate including a first region and a second region;
patterning the mold structure to form first vertical holes extending into the mold structure on the first region and second vertical holes extending into the mold structure on the second region;
forming first vertical structures in the first vertical holes and second vertical structures in the second vertical holes, wherein each of the first and second vertical structures comprises a data storage pattern and a vertical semiconductor pattern;
removing the vertical semiconductor patterns of the second vertical structures to expose the data storage patterns in the second vertical holes; and
forming insulation structures in the second vertical holes in which the data storage patterns are exposed.

### Claim 6 (depends on 5)

The method of claim 5, wherein the data storage patterns of the first and second vertical structures comprise the same material.

### Claim 7 (depends on 5)

The method of claim 5, wherein each of the data storage patterns comprises a blocking insulation layer, a charge storage layer, and a tunnel insulation layer that are sequentially stacked on an inner wall of each of the first and second vertical holes.

### Claim 8 (depends on 5)

The method of claim 5, wherein removing the vertical semiconductor patterns of the second vertical structures comprises exposing a top surface of the substrate.

### Claim 9 (depends on 5)

The method of claim 5, wherein the insulation structures directly contact the substrate.

### Claim 10 (depends on 5)

The method of claim 5, wherein the mold structure comprises sacrificial layers and insulation layers that are alternately stacked on the substrate, and
the method further comprises, after forming the insulation structures, replacing the sacrificial layers with electrodes.

### Claim 11

A three-dimensional semiconductor memory device, comprising:
a semiconductor layer including a first region and a second region;
a plurality of first vertical structures on the first region and extending in a first direction perpendicular to a top surface of the semiconductor layer; and
a plurality of second vertical structures on the second region and extending in the first direction,
wherein each of the first vertical structures comprises:
a vertical semiconductor pattern extending in the first direction and contacting the semiconductor layer; and
a first data storage pattern surrounding a periphery of the vertical semiconductor pattern, and
wherein each of the second vertical structures comprises:
an insulation structure extending in the first direction and contacting the semiconductor layer;
a second data storage pattern surrounding a periphery of the insulation structure; and
a protruding portion extending in the first direction and in a second direction perpendicular to the first direction.

### Claim 12 (depends on 11)

The device of claim 11, further comprising an electrode structure including electrodes vertically stacked on the semiconductor layer, wherein the electrode structure comprises a stepwise structure on the second region, wherein each of the electrodes comprises a pad that constitutes the stepwise structure on the second region, and wherein the second vertical structures extend into the pad of each of the electrodes.

### Claim 13 (depends on 12)

The device of claim 12, further comprising cell contact plugs coupled to the pads of the electrodes on the second region, wherein each of the cell contact plugs is between adjacent second vertical structures.

### Claim 14 (depends on 13)

The device of claim 13, wherein each of the cell contact plugs is partially surrounded by the second vertical structures, in a plan view.