# US 2020/0402984 A1 · Stacked-nanosheet semiconductor structures

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- Number: US 2020/0402984 A1
- Document ID: US20200402984A1
- Status: Published application
- Kind: A1
- Application number: 16/446,752
- Filed: 2019-06-20
- Published: 2020-12-24
- Earliest claimed: 2019-06-20
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Alexander Reznicek; Bahman Hekmatshoartabari; Karthik Balakrishnan; Jeng-Bang Yau
- Web page: https://patentgrep.com/patent/US20200402984A1

## CPC

- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/697: {having trapping at multiple separated sites, e.g. multi-particles trapping sites}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/69396: {the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/642: {Chemical etching}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Semiconductor structures and methods of making the same. The semiconductor structures including at least two vertically stacked nanosheet devices. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (HNS devices) that are stacked vertically, on top of each other, relative to a top surface of a substrate. The plurality of HNS devices including a first HNS device and a second HNS device that each have source and drain structures.

## Claims

### Claim 1

A semiconductor structure that includes an erasable programmable read-only memory (EPROM) bit cell, the EPROM bit cell comprising:
a stacked pair of field-effect transistors including a first field-effect transistor (FET) and a second FET, the first FET having a first gate terminal connected to a word-line and a first source/drain terminal connected to a select-line;
wherein: the first and second FET are horizontal nano-sheet FETs (HNS-FETs).

### Claim 2

(canceled)

### Claim 3 (depends on 1)

The EPROM bit cell of claim 1, wherein the first FET is an n-FET.

### Claim 4

(canceled)

### Claim 5 (depends on 1)

The EPROM bit cell of claim 1, wherein a second source/drain terminal of the first FET is connected to a first source/drain terminal of the second FET.

### Claim 6 (depends on 3)

The EPROM bit cell of claim 3, wherein the second FET is a p-FET.

### Claim 7 (depends on 1)

The EPROM bit cell of claim 1, wherein a second gate terminal of the second FET is an electrically floating gate.

### Claim 8 (depends on 5)

The EPROM bit cell of claim 5, wherein a second source/drain terminal of the second FET is connected to a bit-line.

### Claim 9 (depends on 7)

The EPROM bit cell of claim 7, wherein the second gate terminal of the second FET is comprised of a storage dielectric.

### Claim 10 (depends on 9)

The EPROM bit cell of claim 9, wherein the storage dielectric includes quantum dots.

### Claim 11 (depends on 9)

The EPROM bit cell of claim 9, wherein the storage dielectric is comprised of silicon oxide having silicon nano-dots within the silicon oxide.

### Claim 12 (depends on 11)

The EPROM bit cell of claim 11, wherein the silicon oxide and the silicon nano-dots comprise an annealed flowable oxide.

### Claim 13

A semiconductor structure including an erasable programmable read-only inverter, the erasable programmable read-only inverter comprising:
a stacked pair of field-effect transistors including a first field-effect transistor (FET) and a second FET, the first FET having a first gate terminal connected to an input line and a first source/drain terminal connected to a first power supply line;
wherein: the first and second FET are horizontal nano-sheet FETs (HNS-FETs).

### Claim at position 14

14-15. (canceled)

### Claim 16 (depends on 14)

The erasable programmable read-only inverter of claim 14, wherein a second source/drain terminal of the first FET is connected to both of (i) a first source/drain terminal of the second FET and (ii) an output line.

### Claim 17 (depends on 16)

The erasable programmable read-only inverter of claim 16, wherein a second gate terminal of the second FET is an electrically floating gate, and a second source/drain terminal of the second FET is connected to a second power supply line.

### Claim 18 (depends on 17)

The erasable programmable read-only inverter of claim 17, wherein the second gate terminal of the second FET is comprised of a storage dielectric.

### Claim 19 (depends on 18)

The erasable programmable read-only inverter of claim 18, wherein the storage dielectric includes quantum dots.

### Claim 20 (depends on 19)

The erasable programmable read-only inverter of claim 19, wherein the storage dielectric is comprised of silicon oxide having silicon nano-dots within the silicon oxide.