# US 2020/0402979 A1 · Tie off device

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- Number: US 2020/0402979 A1
- Document ID: US20200402979A1
- Status: Published application
- Kind: A1
- Application number: 16/879,166
- Filed: 2020-05-20
- Published: 2020-12-24
- Earliest claimed: 2019-06-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shao-Lun Chien; Ting-Wei Chiang; Hui-Zhong Zhuang; Pin-Dai Sue
- Web page: https://patentgrep.com/patent/US20200402979A1

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10W 10/051: {of isolation region based on field-effect}
- H10W 10/50: Isolation regions based on field-effect
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/427: {Power or ground buses}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/931: {FET isolation}
- H10D 89/10: Integrated device layouts
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit device includes a first power rail, a first active area extending in a first direction, and a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction. A first transistor includes the first active area and a first one of the gates. The first transistor has a first threshold voltage (VT). A second transistor includes the first active area and a second one of the gates. The second transistor has a second VT different than the first VT. A tie-off transistor is positioned between the first transistor and the second transistor, and includes the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

## Claims

### Claim 1

An integrated circuit device, comprising:
a first power rail;
a first active area extending in a first direction;
a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction;
a first transistor including the first active area and a first one of the gates, the first transistor having a first threshold voltage (VT);
a second transistor including the first active area and a second one of the gates, the second transistor having a second VT different than the first VT; and
a tie-off transistor positioned between the first transistor and the second transistor, the tie-off transistor including the first active area and a third one of the gates, wherein the third gate is connected to the first power rail.

### Claim 2 (depends on 1)

The integrated circuit device of claim 1, wherein the third gate is connected to the first power rail by a first conductive via.

### Claim 3 (depends on 1)

The integrated circuit device of claim 1, wherein the first active area includes a fin.

### Claim 4 (depends on 1)

The integrated circuit device of claim 1, wherein the tie-off transistor is a PMOS transistor, and where the first power rail is a VDD power rail.

### Claim 5 (depends on 1)

The integrated circuit device of claim 1, wherein the tie-off transistor is an NMOS transistor, and where the first power rail is a VSS power rail.

### Claim 6 (depends on 4)

The integrated circuit device of claim 4, wherein the first and second transistors are PMOS transistors.

### Claim 7 (depends on 5)

The integrated circuit device of claim 5, wherein the first and second transistors are NMOS transistors.

### Claim 8 (depends on 6)

The integrated circuit device of claim 6, wherein the plurality of gates are poly gates, the integrated circuit further comprising:
a VSS power rail;
a second active area extending in a first direction, wherein the plurality of poly gates contact the second active area;
a first NMOS transistor including the second active area and the first poly gate, the first NMOS transistor having the first VT;
a second NMOS transistor including the second active area and the second poly gate, the second NMOS transistor having the second VT; and
an NMOS tie-off transistor positioned between the first NMOS transistor and the second NMOS transistor, the NMOS tie-off transistor including the first active area and the third poly gate, wherein the third poly gate is connected to the VSS power rail, and wherein the third poly gate includes a cut poly between the first and second active areas.

### Claim 9 (depends on 8)

The integrated circuit device of claim 8, wherein the third poly gate is connected to the VSS power rail by a second conductive via.

### Claim 10 (depends on 9)

The integrated circuit device of claim 9, wherein the third poly gate is connected to the VSS power rail by a metal layer and a third conductive via.

### Claim 11

A semiconductor device, comprising:
a first power rail;
a second power rail;
a first fin extending in a first direction;
a first PMOS transistor including the first fin and a first gate, the first PMOS transistor having a first threshold voltage (VT), the first gate extending in a second direction perpendicular to the first direction;
a second PMOS transistor including the first fin and a second gate extending in the second direction, the second PMOS transistor having a second VT different than the first VT, and wherein the second gate is connected to the first power rail;
a second fin extending in the first direction;
a first NMOS transistor including the second fin and the first gate, the first NMOS transistor having the first VT;
a second NMOS transistor including the second fin and the second gate, the second NMOS transistor having the second VT, and wherein the second gate is connected to the second power rail.

### Claim 12 (depends on 11)

The integrated circuit device of claim 11, wherein the first gate is connected to the second power rail, and wherein the second gate is connected to the first power rail through the first PMOS transistor.

### Claim 13 (depends on 11)

The integrated circuit device of claim 11, wherein the first gate is connected to the first power rail, and wherein the second gate is connected to the second power rail through the first NMOS transistor.

### Claim 14 (depends on 12)

The integrated circuit device of claim 12, wherein the second gate is connected to the first PMOS transistor through a metal layer extending in the first direction and a metal strip extending in the second direction.

### Claim 15 (depends on 11)

The integrated circuit device of claim 11, further comprising:
a third PMOS transistor including the first fin and a third gate, the third PMOS transistor having the second VT, wherein the second PMOS transistor is between the first and third PMOS transistors;
a third NMOS transistor including the first fin and the third gate, the third NMOS transistor having the second VT, wherein the second NMOS transistor is between the first and third NMOS transistors.

### Claim 16 (depends on 11)

The integrated circuit device of claim 11, wherein the first, second and third gates comprise respective first, second and third poly gates, and wherein the second poly gate includes a cut poly between the first and second fins, and wherein the second poly gate is directly connected to the first power rail.

### Claim 17

A method, comprising:
forming a first active area on a substrate, the first active area including a first threshold voltage (VT) region and a second VT region;
forming a first gate contacting the first VT region of the first active area to form a first transistor having a first VT;
forming a second gate contacting the second VT region of the first active area to form a second transistor having a second VT different than the first VT;
forming a third gate contacting the first active area between the first gate and the second gate to form a tie-off transistor positioned between the first transistor and the second transistor; and
connecting the third gate to a power rail to maintain the tie-off transistor in an off state.

### Claim 18 (depends on 17)

The method of claim 17, wherein the tie-off transistor is a PMOS transistor and wherein connecting the third gate to the power rail to maintain the tie-off transistor in the off state includes connecting the third gate to a VDD power rail.

### Claim 19 (depends on 18)

The method of claim 18, wherein connecting the third gate to the VDD power rail includes providing a conductive via extending between the third gate and the VDD power rail.

### Claim 20 (depends on 18)

The method of claim 18, wherein the first and second transistors and the tie-off transistor are PMOS transistors, the method further comprising:
forming a second active area on the substrate, the second active area including the first VT region and the second VT region;
forming the first gate to further contact second active area to form a first NMOS transistor having the first VT;
forming the second gate to further contact the second active area to form a second NMOS transistor having the second VT;
forming the third gate to further contact the second active area to form an NMOS tie-off transistor positioned between the first NMOS transistor and the second NMOS transistor; and
connecting the third gate to a second power rail to maintain the NMOS tie-off transistor in an off state.