# US 2020/0402918 A1 · Integrated Circuit Saw Bow Break Point

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- Number: US 2020/0402918 A1
- Document ID: US20200402918A1
- Status: Published application
- Kind: A1
- Application number: 16/444,322
- Filed: 2019-06-18
- Published: 2020-12-24
- Earliest claimed: 2019-06-18
- Assignees: NXP B.V.
- Applicants: NXP B.V.
- Inventors: Antonius Hendrikus Jozef Kamphuis; Johannes Cobussen; Christian Zenz; Guido Albermann
- Web page: https://patentgrep.com/patent/US20200402918A1

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 72/00: Interconnections or connectors in packages
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A saw bow is provided and designed such that the conductors of the saw bow will break at a predictable location when using modern dicing techniques. This results in a break in the circuit provided by the saw bow, with any exposed conductors not being on the die side. Further, by providing a known breaking point in the saw bow, modern dicing techniques such as plasma dicing can be used, thereby allowing for the saw lane to be made narrower, which will in turn increase the number of wafers that can be included on a wafer.

## Claims

### Claim 1

A semiconductor wafer having a plurality of semiconductor device die arranged in a grid pattern, the semiconductor wafer comprising:
a first semiconductor device die;
a second semiconductor device die, neighboring the first semiconductor device die in the grid pattern and separated from the first semiconductor device die by a dicing lane; and
a first conductor extending from a side of the first semiconductor device die into the dicing lane and extending toward the second semiconductor device die, entering the second semiconductor device die, and ending within a seal ring region of the second semiconductor device die, wherein the first conductor is formed such that a first region of the first conductor located nearer to the first semiconductor device die in the dicing lane has a lower tensile strength than a second region of the first conductor located nearer to the second semiconductor device die.

### Claim 2 (depends on 1)

The semiconductor wafer of claim 1 further comprising:
a second conductor extending from the side of the first semiconductor device die into the dicing lane and extending toward the second semiconductor device die, entering the second semiconductor device die, and ending within the seal ring region of the second semiconductor device die, wherein
the second conductor is formed such that a first region of the second conductor located nearer to the first semiconductor device die has a lower tensile strength than a second region of the second conductor located nearer to the second semiconductor device die, and
the second conductor is parallel to the first conductor; and
a third conductor that electrically couples the first conductor to the second conductor at the ends of the first and second conductors within the seal ring region of the second semiconductor device die.

### Claim 3 (depends on 2)

The semiconductor wafer of claim 2, wherein a distance between the first conductor and the second conductor is about 2 μm.

### Claim 4 (depends on 2)

The semiconductor wafer of claim 2 wherein the first and second conductors are within a same metal layer of one or more metal layers implemented on the semiconductor wafer.

### Claim 5 (depends on 2)

The semiconductor wafer of claim 2, wherein
the first and second conductors are within different metal layers of one or more metal layers implemented on the semiconductor wafer, and
the second conductor is located above the first conductor.

### Claim 6 (depends on 1)

The semiconductor wafer of claim 1 wherein the first conductor is formed such that the first region of the first conductor has a lower tensile strength than the second region of the first conductor by virtue of the first conductor having a narrower width in the first region than the second region.

### Claim 7 (depends on 6)

The semiconductor wafer of claim 6, wherein
the first conductor comprises a third region between the first and second regions,
the third region has a width of approximately 0.3 μm, and
the first region has a width of 85% or less than that of the third region.

### Claim 8 (depends on 7)

The semiconductor wafer of claim 7, wherein the second region has a width of greater than 0.3 μm.

### Claim 9 (depends on 1)

The semiconductor wafer of claim 1, wherein the first conductor is formed such that the first region of the first conductor has a lower tensile strength than the second region of the first conductor by virtue of the second region of the first conductor comprising an approximate shape of an isosceles triangle,
a base of the isosceles triangle is the end of the first conductor nearer to the second semiconductor device die,
the base of the isosceles triangle is approximately three times a width of the first conductor in the first region, and
a tip of the isosceles triangle is subsumed within the first conductor toward the first region.

### Claim 10

A method of providing a saw bow to a semiconductor device die on a wafer, the method comprising:
forming integrated circuitry within one or more metal layers on a wafer, wherein
the integrated circuitry is arranged in a grid pattern of a plurality of device die regions including a first semiconductor device die region and a second semiconductor device die region, and
the first semiconductor device die region is separated from the second semiconductor device die region by a dicing lane; and
forming a first conductor extending from a side of the first semiconductor device die region into the dicing lane and toward the second semiconductor device die region, wherein
the first conductor is coupled to a metal layer of the one or more metal layers,
the first conductor ends within a seal ring region of the second semiconductor device die region,
the first conductor comprises a first region located nearer to the first semiconductor device die region and a second region located nearer to the second semiconductor device die region, and
the first conductor comprises a lower tensile strength in the first region than the second region.

### Claim 11 (depends on 10)

The method of claim 10 further comprising:
forming a second conductor extending from a side of the first semiconductor device die region into the dicing lane and toward the second semiconductor device die region, wherein
the second conductor is coupled to the metal layer,
the second conductor ends within the seal ring of the second semiconductor device die region,
the second conductor comprises a first region located nearer to the first semiconductor device die region and a second region located nearer to the second semiconductor device die region;
the second conductor comprises a lower tensile strength in the first region than the second region; and
forming a third conductor to electrically couple the first conductor to the second conductor at the ends of the first and second conductors in the seal ring of the second semiconductor device die region.

### Claim 12 (depends on 10)

The method of claim 10, wherein the first semiconductor device die region comprises another metal layer of the one or more metal layers, the method further comprising:
forming a second conductor extending from a side of the first semiconductor device die region into the dicing lane and toward the second semiconductor device die region, wherein
the second conductor is coupled to the other metal layer,
the second conductor ends in or near the seal ring of the second semiconductor device die region,
the second conductor comprises a first region located nearer to the first semiconductor device die and a second region located nearer to the second semiconductor device die,
the second conductor comprises a lower tensile strength in the first region than the second region;
the second conductor is above the first conductor and approximately parallel to the first conductor and about the length of the first conductor; and
forming a third conductor to electrically couple the first conductor to the second conductor in the seal ring of the second semiconductor device die region.

### Claim 13 (depends on 12)

The method of claim 12, wherein the third conductor is a metal-filled via.

### Claim 14 (depends on 10)

The method of claim 10 wherein said forming the first conductor such that the first conductor comprises a lower tensile strength in the first region than the second region further comprises:
forming the first conductor to have a narrower width in the first region than in the second region.

### Claim 15 (depends on 10)

The method of claim 10 further comprising:
etching wafer material from the dicing lane to perform plasma dicing of the first semiconductor device die from the second semiconductor device die region; and
subjecting the first conductor to a tensile force after said etching, wherein the tensile force is sufficient to break the first conductor in the first region.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first conductor forms at least a part of a conductive pathway to test circuitry formed within the first semiconductor device die region and the conductive pathway is eliminated upon the breaking of the first conductor.

### Claim 17

A semiconductor device die having integrated circuitry implemented in one or more metal layers, the semiconductor device die comprising:
a first conductor exposed within a recess formed in a first sidewall of the semiconductor device die, wherein the first conductor has a first width; and
a second conductor exposed at a surface of a second sidewall of the semiconductor device die, wherein
the second sidewall is opposite the first sidewall,
the second conductor has a second width, and
the second width is larger than the first width.

### Claim 18 (depends on 17)

The semiconductor device die of claim 17, further comprising:
a third conductor exposed within another recess formed in the first sidewall of the semiconductor device die.

### Claim 19 (depends on 18)

The semiconductor device die of claim 18, wherein
the first conductor and the third conductor are formed within a same metal layer of the semiconductor device die.

### Claim 20 (depends on 18)

The semiconductor device die of claim 18, wherein
the first conductor and the third conductors are formed within different metal layers of the semiconductor device die.