# US 2020/0402913 A1 · Connecting multiple chips using an interconnect device

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- Number: US 2020/0402913 A1
- Document ID: US20200402913A1
- Status: Published application
- Kind: A1
- Application number: 16/905,766
- Filed: 2020-06-18
- Published: 2020-12-24
- Earliest claimed: 2019-06-19
- Assignees: Invensas Corporation
- Applicants: Invensas Corporation
- Inventors: Javier A. Delacruz; Belgacem Haba
- Web page: https://patentgrep.com/patent/US20200402913A1

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 72/0198: {batch processes}
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/095: {of vias therein}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Techniques are disclosed herein for connecting multiple chips using an interconnect device. In some configurations, one or more interconnect areas on a chip can be located adjacent to each other such that at least a portion of an edge of a first interconnect area is located adjacent to an edge of a second interconnect area. For example, an interconnect area can be located at a corner of a chip such that one or more edges of the interconnect area lines up with one or more edges of an interconnect area of another chip. The chip including at least one interconnect area can also be positioned and directly bonded to the interconnect device using other layouts, such as but not limited to a pinwheel layout. In some configurations more than one interconnect area can be included on a chip.

## Claims

### Claim 1

A device comprising:
an interconnect device;
a first chip comprising a first interconnect area adjacent to an edge of the first chip; and
a second chip comprising a second interconnect area adjacent to an edge of the second chip,
wherein the first interconnect area is directly bonded to a first portion of the interconnect device, and positioned adjacent to the second interconnect area that is directly bonded to a second portion of the interconnect device, such that electrical connections are created between the first interconnect area and the second interconnect area.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first interconnect area has a pitch of less than twenty microns.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first chip comprises a third interconnect area; and the first interconnect area is located on a first edge of the first chip and the third interconnect area is located on a second edge of the first chip.

### Claim 4 (depends on 3)

The device of claim 3, further comprising a third chip comprising a fourth interconnect area adjacent to an edge of the third chip,
wherein the third interconnect area is directly bonded to a third portion of the interconnect device, and positioned adjacent to the fourth interconnect area that is directly bonded to a fourth portion of the interconnect device, such that electrical connections are created between the third interconnect area and the fourth interconnect area.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first and second interconnect areas have pads of a first size and a first pitch, the device further comprising regions on the first chip and the second chip that have pads of a second size and a second pitch, the pads of a second size being larger than the pads of the first size and the second pitch being larger than the first pitch.

### Claim 6 (depends on 5)

The device of claim 5, wherein the interconnect device is incorporated in a structure, the structure comprising pass through interconnects in regions not occupied by the interconnect device, the pads of the second size coupled with the pass though interconnects.

### Claim 7 (depends on 6)

The device of claim 6, wherein the structure comprises at least one semiconductor or dielectric region, the pass through interconnects comprising vias that extend through the semiconductor or dielectric region.

### Claim 8

A device comprising:
an interconnect device that includes a first bonding area that is adjacent to a second bonding area;
a first chip that includes a first interconnect area with a pitch of less than nine microns that is bonded to the first bonding area; and
a second chip that includes a second interconnect area with a pitch of less than nine microns that is bonded to the second bonding area, wherein electrical connections are created between the first interconnect area and the second interconnect area.

### Claim 9 (depends on 8)

The device of claim 8, wherein the first interconnect area is located at a first corner of the first chip and the second interconnect area is located at a second corner of the second chip.

### Claim 10 (depends on 8)

The device of claim 8, wherein the first chip includes a third interconnect area adjacent to an edge of the first chip and the second chip includes a fourth interconnect area adjacent to a second edge of the second chip.

### Claim 11 (depends on 8)

The device of claim 8, wherein the first chip is positioned on the interconnect device at a first orientation and the second chip is positioned on the interconnect device at a second orientation that is rotated relative to the first chip such that the first interconnect area is adjacent to the second interconnect area.

### Claim 12 (depends on 8)

The device of claim 8, wherein the first and second interconnect areas have pads of a first size and a first pitch, the device further comprising regions on the first chip and the second chip that have pads of a second size and a second pitch, the pads of a second size being larger than the pads of the first size and the second pitch being larger than the first pitch.

### Claim 13 (depends on 12)

The device of claim 12, wherein the interconnect device is incoporated in a structure, the structure comprising pass through interconnects in regions not occupied by the interconnect device, the pads of the second size coupled with the pass though interconnects.

### Claim 14 (depends on 12)

The device of claim 12, wherein the electrical connections comprise native interconnects.

### Claim 15

A method comprising:
creating a first chip that includes a first interconnect area adjacent to a first edge of the first chip; and
creating a second chip that includes a second interconnect area adjacent to a second edge of the second chip;
directly bonding the first interconnect area to a first portion of an interconnect device; and
directly bonding the second interconnect area to a second portion of the interconnect device such that electrical connections are created between the first interconnect area and the second interconnect area, wherein the first portion of the interconnect device is adjacent to the second portion of the interconnect device.

### Claim 16 (depends on 15)

The method of claim 15, wherein creating the first chip comprises creating the first interconnect area to have a pitch less than 20 microns.

### Claim 17 (depends on 15)

The method of claim 15, wherein creating the first chip comprises positioning the first interconnect area on a first edge the first chip and positioning a third interconnect area of the first chip on a third edge of the first chip.

### Claim 18 (depends on 15)

The method of claim 15, wherein creating the first chip comprises:
creating first pads of a first size and a first pitch; and
creating second pads of a second size and a second pitch,
the second pads of the second size being larger than the first pads of the first size and the second pitch being larger than the first pitch.

### Claim 19 (depends on 18)

The method of claim 18, further comprising incorporating the interconnect device within a structure, the structure comprising pass through interconnects in regions not occupied by the interconnect device, the second pads of the second size coupled with the pass though interconnects.

### Claim 20 (depends on 19)

The method of claim 19, further comprising creating vias in the structure that extend through at least one semiconductor or dielectric region.