# US 2020/0402906 A1 · Semiconductor device having a stacked structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0402906 A1 - Document ID: US20200402906A1 - Status: Published application - Kind: A1 - Application number: 16/732,772 - Filed: 2020-01-02 - Published: 2020-12-24 - Earliest claimed: 2019-06-20 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: GEUNWON LIM - Web page: https://patentgrep.com/patent/US20200402906A1 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device includes a substrate having a cell array region and a pad region, a stack structure including gate electrodes and mold insulating layers alternately stacked on the substrate and having a staircase shape in the pad region, first separation regions penetrating the stack structure in the pad region, extending in a first direction, and including first and second dummy insulating layers, the first dummy insulating layers covering side walls of the first separation regions and including horizontal portions covering portions of the gate electrodes, and the second dummy insulating layers disposed between the first dummy insulating layers, extending portions extending towards the mold insulating layers from the first dummy insulating layers in a second direction perpendicular to the first direction, second separation regions dividing the stack structure and extending in the first direction, and cell contact plugs penetrating the horizontal portions and connected to the gate electrodes. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate having a cell array region and a pad region; a stack structure including gate electrodes and mold insulating layers alternately stacked on the substrate and having a staircase shape in the pad region; a plurality of first separation regions penetrating the stack structure vertically in the pad region, extending in a first direction, and including first dummy insulating layers and second dummy insulating layers, wherein the first dummy insulating layers cover internal side walls of the plurality of first separation regions and include horizontal portions covering portions of upper surfaces of upper gate electrodes of the gate electrodes, and the second dummy insulating layers are disposed between the first dummy insulating layers; extending portions extending towards the mold insulating layers from the first dummy insulating layers in a second direction perpendicular to the first direction; a plurality of second separation regions dividing the stack structure into a plurality of regions and extending in the first direction; and cell contact plugs penetrating the horizontal portions in the second dummy insulating layers and connected to the gate electrodes. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the extending portions include a first extending portion and a second extending portion disposed on different levels in a third direction substantially perpendicular to an upper surface of the substrate, and one end of the first extending portion and one end of the second extending portion are disposed in different positions in the second direction. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the first dummy insulating layers are in contact with the extending portions through an external side surface of the first dummy insulating layers. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein each of the extending portions has a recess portion having a concave shape in the second direction. ### Claim 5 (depends on 1) The semiconductor device of claim 1, further comprising: an interlayer insulating layer covering the stack structure in the pad region, wherein the plurality of first separation regions include first upper separation regions in contact with the interlayer insulating layer and first lower separation regions in contact with the stack structure, and wherein a first width of each of the first upper separation regions taken in the second direction is greater than a second width of each of the first lower separation regions taken in the second direction. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the plurality of second separation regions extend further than the plurality of first separation regions in the first direction on the substrate. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the plurality of second separation regions are disposed in the cell array region and in the pad region, and the plurality of first separation regions are disposed in the pad region. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the extending portions are disposed below the cell contact plugs. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the cell contact plugs include first and second cell contact plugs penetrating one of the second dummy insulating layers and having heights different from each other in a third direction substantially perpendicular to an upper surface of the substrate. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein a difference in heights between the first and second cell contact plugs is substantially the same as a sum of a thickness of one of the gate electrodes and a thickness of one of the mold insulating layers. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein a gap between the first dummy insulating layers decreases towards an upper surface of the substrate in the plurality of first separation regions. ### Claim 12 (depends on 1) The semiconductor device of claim 1, further comprising: at least one sacrificial layer disposed between the horizontal portions and the extending portions and including a material different from a material of the gate electrodes. ### Claim 13 (depends on 1) The semiconductor device of claim 1, further comprising: a peripheral circuit region provided below the substrate, and including circuit elements electrically connected to the gate electrodes. ### Claim 14 (depends on 13) The semiconductor device of claim 13, further comprising: a through-wiring electrically connecting the cell array region to the peripheral circuit region in the pad region, wherein the through-wiring is electrically connected to the cell contact plugs. ### Claim 15 A semiconductor device, comprising: a substrate having a cell array region and a pad region; a stack structure including gate electrodes and mold insulating layers having a staircase shape in the pad region; an interlayer insulating layer covering the stack structure in the pad region; a plurality of first separation regions penetrating the stack structure and the interlayer insulating layer in the pad region, wherein the plurality of first separation regions include first insulating layers covering one end of the gate electrodes and extending in a direction substantially perpendicular to an upper surface of the substrate, and second insulating layers disposed between the first insulating layers; a plurality of second separation regions dividing the stack structure into a plurality of regions on the substrate and extending in a first direction; at least one dummy channel disposed between the plurality of first separation regions and the plurality of second separation regions; and cell contact plugs penetrating the first insulating layers and connected to the gate electrodes in the plurality of first separation regions. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein the at least one dummy channel is spaced apart from the cell contact plugs. ### Claim 17 (depends on 15) The semiconductor device of claim 15, wherein the first insulating layers include a material different from a material of the mold insulating layers. ### Claim 18 (depends on 15) The semiconductor device of claim 15, wherein one or more of the plurality of first separation regions are disposed between the plurality of second separation regions. ### Claim 19 A semiconductor device, comprising: a substrate having a cell array region and a pad region; a stack structure including gate electrodes and mold insulating layers alternately stacked on the substrate and having a staircase shape in the pad region; an interlayer insulating layer covering the stack structure in the pad region; dummy insulating layers dividing the stack structure and the interlayer insulating layer into a plurality of regions and including a material different from a material of the interlayer insulating layer; extending portions in contact with the dummy insulating layers in the stack structure, and spaced apart from one another in a direction substantially perpendicular to an upper surface of the substrate between the gate electrodes; and cell contact plugs disposed in the dummy insulating layers and connected to the gate electrodes. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein each of the extending portions has a recess portion having a concave shape.