# US 2020/0402879 A1 · Semiconductor package structure and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0402879 A1 - Document ID: US20200402879A1 - Status: Published application - Kind: A1 - Application number: 16/448,970 - Filed: 2019-06-21 - Published: 2020-12-24 - Earliest claimed: 2019-06-21 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Chi Sheng TSENG; Lu-Ming LAI; Hui-Chung LIU - Web page: https://patentgrep.com/patent/US20200402879A1 ## CPC - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 74/127: {characterised by arrangements for sealing or adhesion} - B06B 1/0629: {Square array} - B81B 7/0077: {Other packages not provided for in groups B81B7/0035 - B81B7/0074} - B81C 1/00158: {Diaphragms, membranes (manufacture process for semi-permeable inorganic membranes B01D67/0039)} - B81C 1/00238: {Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure} - B81C 1/00309: {suitable for fluid transfer from the MEMS out of the package or vice versa, e.g. transfer of liquid, gas, sound} - H10W 74/016: {using moulds} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/124: {the encapsulations having cavities other than that occupied by chips} - H10W 76/60: Seals - B81B 7/0032: {Packages or encapsulation (processes for packaging MEMS B81C1/00261; packaging of smart-MEMS B81C1/0023)} - B81B 2201/0271: Resonators; ultrasonic resonators - B81B 2207/07: Interconnects - B81C 2203/035: Soldering - B81C 2203/0792: Forming interconnections between the electronic processing unit and the micromechanical structure - H10W 74/014: {using batch processing} - H10W 74/10: characterised by their shape or disposition - H10W 90/722: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B06B: METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, {e.g.} FOR PERFORMING MECHANICAL WORK IN GENERAL (for particular applications, see the relevant subclasses, e.g. B07B1/40, B23Q17/12, B24B31/06; measurement of mechanical vibrations G01H; in direction finding, locating, distance or velocity measuring G01S; {generating seismic energy G01V1/02}; control of mechanical vibrations in general G05D; sound-producing devices, e.g. bells, sirens, whistles G10K, {e.g. methods or devices for transmitting, conducting, or directing sound in general G10K11/00}; generation of electrical oscillations H03B; electromechanical resonators in general H03H; electromechanical transducers {for communication techniques, e.g. microphones, speakers} H04R) - B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00) - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) ## Abstract A semiconductor package structure includes a substrate; a first die on the substrate, wherein an active surface of the first die is facing away from the substrate; a second die on the active surface of the first die, electrically connected to the first die through a plurality of conductive terminals; and a sealing structure on the active surface of the first die, surrounding the plurality of conductive terminals and abutting the second die thereby forming a cavity between the first die and the second die. A method for manufacturing the semiconductor package structure is also provided. ## Claims ### Claim 1 A semiconductor package structure, comprising: a substrate; a first die on the substrate, wherein an active surface of the first die is facing away from the substrate; a second die on the active surface of the first die, electrically connected to the first die through a plurality of conductive terminals; and a sealing structure on the active surface of the first die, surrounding the plurality of conductive terminals and abutting the second die thereby forming a cavity between the first die and the second die. ### Claim 2 (depends on 1) The semiconductor package structure of claim 1, wherein the cavity is an air cavity. ### Claim 3 (depends on 1) The semiconductor package structure of claim 1, wherein the plurality of conductive terminals comprises solder joints. ### Claim 4 (canceled) ### Claim 5 (depends on 1) The semiconductor package structure of claim 1, wherein a vertical projection area of the second die is smaller than a vertical projection of the first die. ### Claim 6 (depends on 1) The semiconductor package structure of claim 1, wherein the second die comprises a piezoelectric micromachined ultrasonic transducer (PMUT). ### Claim 7 (depends on 1) The semiconductor package structure of claim 1, further comprising a first encapsulant at least encapsulating the second die by covering a back surface of the second die and the sealing structure. ### Claim 8 (depends on 7) The semiconductor package structure of claim 7, further comprising a second encapsulant at least encapsulating the first die and surrounding the plurality of conductive terminals. ### Claim 9 (depends on 8) The semiconductor package structure of claim 8, wherein the second encapsulant further surrounds the first encapsulant. ### Claim 10 (depends on 7) The semiconductor package structure of claim 7, wherein the first encapsulant comprises silicone. ### Claim 11 (canceled) ### Claim 12 A semiconductor package structure, comprising: a substrate; a first die on the substrate; a second die on the first die, the second die comprising a plurality of cell regions, each of the cell regions comprising a membrane portion, a receiving portion connected to the membrane portion, and a transmission portion connected to the membrane portion; and a sealing structure surrounding the plurality of cell regions. ### Claim 13 (depends on 12) The semiconductor package structure of claim 12, wherein the sealing structure surrounds and in contact with an edge of the second die. ### Claim 14 (depends on 12) The semiconductor package structure of claim 12, wherein the transmission portion and the receiving portion each comprises a conductive terminal electrically connected to an active surface of the first die. ### Claim 15 (depends on 13) The semiconductor package structure of claim 13, wherein the sealing structure, the first die, and the second die form an air cavity accommodating the conductive terminal. ### Claim 16 (depends on 12) The semiconductor package structure of claim 12, further comprising a first encapsulant at least encapsulating the second die. ### Claim 17 (depends on 16) The semiconductor package structure of claim 16, further comprising a second encapsulant at least surrounding the first die. ### Claim 18 (canceled) ### Claim 19 (canceled) ### Claim 20 (canceled) ### Claim 21 A semiconductor package structure, comprising: a substrate; a first die on the substrate, wherein an active surface of the first die is facing away from the substrate; a second die on the active surface of the first die, the second die comprising a plurality of cell regions and electrically connected to the first die; and a sealing structure on the active surface of the first die, the sealing structure surrounding the plurality of cell regions thereby forming a cavity for the plurality of cell regions. ### Claim 22 (depends on 21) The semiconductor package structure of claim 21, wherein the second die is electrically connected to the first die through a plurality of conductive terminals. ### Claim 23 (depends on 22) The semiconductor package structure of claim 22, wherein the sealing structure is in contact with an edge of the second die and surrounds the plurality of conductive terminals. ### Claim 24 (depends on 23) The semiconductor package structure of claim 23, wherein the sealing structure, the first die, and the second die form the cavity for the plurality of cell regions. ### Claim 25 (depends on 24) The semiconductor package structure of claim 24, wherein the plurality of conductive terminals comprises solder joints.