# US 2020/0402807 A1 · Semiconductor FinFET Device and Method

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- Number: US 2020/0402807 A1
- Document ID: US20200402807A1
- Status: Published application
- Kind: A1
- Application number: 17/012,525
- Filed: 2020-09-04
- Published: 2020-12-24
- Earliest claimed: 2018-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Yu Wang
- Web page: https://patentgrep.com/patent/US20200402807A1

## CPC

- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/57: the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10P 50/283: {by chemical means}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes depositing a mask layer over a semiconductor substrate, etching the mask layer to form a patterned mask, wherein a sidewall of the patterned mask includes a first sidewall region, a second sidewall region, and a third sidewall region, wherein the first sidewall region is farther from the semiconductor substrate than the second sidewall region and the second sidewall region is farther from the semiconductor substrate than the third sidewall region, wherein the second sidewall region protrudes laterally from the first sidewall region and from the third sidewall region, etching the semiconductor substrate using the patterned mask to form fins, forming a gate stack over the fins, and forming source and drain regions in the fin adjacent the gate stack.

## Claims

### Claim 1

A semiconductor device comprising:
a fin extending from an upper surface of a substrate, wherein the fin comprises a first material, wherein the sidewalls of the fin have a first roughness;
a film extending along the sidewalls of the fin, wherein the film comprises a second material, wherein outer surfaces of the film have a second roughness that is greater than the first roughness;
a gate stack over the film and the fin; and
an epitaxy region on the fin, wherein the epitaxy region is adjacent the gate stack.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the film extends along the upper surface the substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the top surface of the fin is free of the film.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second material is different than the first material.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second material is polysilicon.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the polysilicon has an average grain size in the range of 0.5 nm to 20 nm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second roughness has a root mean square (RMS) value in the range of 0.5 nm to 20 nm.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the film has an average thickness in the range of 5 nm to 50 nm.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the film is level with a top surface of the fin.

### Claim 10

A device comprising:
a first fin protruding from a semiconductor substrate;
a second fin protruding from the semiconductor substrate, wherein the second fin is adjacent the first fin;
a roughening layer extending along a first sidewall surface of the first fin, along a second sidewall surface of the second fin, and over the semiconductor substrate, wherein the roughening layer has a root mean square (RMS) roughness value of at least 0.5 nm;
an isolation region on the roughening layer, wherein the isolation surrounds the first fin and surrounds the second fin;
a gate stack over the first fin, along the first sidewall surface, over the second fin, and along the second sidewall surface; and
a first epitaxial source/drain region in the first fin adjacent the gate stack and a second epitaxial source/drain region in the second fin adjacent the gate stack.

### Claim 11 (depends on 10)

The device of claim 10, wherein the gate stack physically contacts the roughening layer along the first sidewall surface and along the second sidewall surface.

### Claim 12 (depends on 10)

The device of claim 10, wherein the gate stack physically contacts top surfaces of the first fin and the second fin.

### Claim 13 (depends on 10)

The device of claim 10, wherein the roughening film extending along the first sidewall surface and along the second sidewall surface protrudes above the isolation region.

### Claim 14 (depends on 10)

The device of claim 10, wherein the material of the roughening film is different from the material of the isolation region.

### Claim 15 (depends on 10)

The device of claim 10, wherein the material of the roughening film is polysilicon.

### Claim 16 (depends on 10)

The device of claim 10, wherein the roughening layer extends continuously from the first sidewall surface to the second sidewall surface.

### Claim 17 (depends on 10)

The device of claim 10, wherein the wherein the first sidewall surface and the second sidewall surface have a root mean square (RMS) roughness value of less than 0.5 nm.

### Claim 18

A device comprising:
a semiconductor fin over a substrate, wherein the semiconductor fin protrudes a first height above a top surface of the substrate;
a polysilicon layer extending on the semiconductor fin from the top surface of the substrate to the first height;
an isolation region surrounding the semiconductor fin and the polysilicon layer; and
a gate structure over the semiconductor fin and on upper surfaces of the polysilicon layer.

### Claim 19 (depends on 19)

The device of claim 19, wherein the polysilicon layer has an average grain size in the range of 0.5 nm to 20 nm.

### Claim 20 (depends on 18)

The device of claim 18, wherein the polysilicon layer extends on the top surface of the substrate.