# US 2020/0402584 A1 · Nonvolatile memory device and method of programming in the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0402584 A1 - Document ID: US20200402584A1 - Status: Published application - Kind: A1 - Application number: 17/007,767 - Filed: 2020-08-31 - Published: 2020-12-24 - Earliest claimed: 2018-11-07 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Yo-Han LEE - Web page: https://patentgrep.com/patent/US20200402584A1 ## CPC - G11C 16/10: Programming or data input circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/20: Initialising; Data preset; Chip identification - G11C 16/24: Bit-line control circuits - G11C 16/32: Timing circuits - H10W 90/00: Package configurations - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 90/792: {between multiple chips} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract In a method of programming in a nonvolatile memory device including a memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, wherein the peripheral circuit region is vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory block in the memory cell region including a plurality of stacks disposed in a vertical direction is provided where the memory block includes cell strings each of which includes memory cells connected in series in the vertical direction between a source line and each of bitlines. A plurality of intermediate switching transistors disposed in a boundary portion between two adjacent stacks in the vertical direction is provided, where the intermediate switching transistors perform a switching operation to control electrical connection of the cell strings, respectively. A boosting operation is performed to boost voltages of channels of the plurality of stacks while controlling the switching operation of the intermediate switching transistors during a program operation with respect to the memory block. Program voltage disturbance and pass voltage disturbance are reduced through control of the switching operation of the intermediate switching transistors. ## Claims ### Claim 1 A method of programming in a nonvolatile memory device, the nonvolatile memory device comprising a memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, wherein the peripheral circuit region is vertically connected to the memory cell region by the first metal pad and the second metal pad, the method comprising: providing a memory block in the memory cell region comprising a plurality of stacks disposed in a vertical direction, each memory block comprising a plurality of cell strings, and each cell string comprising a plurality of memory cells connected in series in the vertical direction between a source line and each of a plurality of bitlines; providing a plurality of intermediate switching transistors disposed in a boundary portion between two adjacent stacks in the vertical direction, the intermediate switching transistors performing a switching operation to control electrical connection of the cell strings, respectively; and performing a boosting operation to boost voltages of channels of the stacks while controlling the switching operation of the intermediate switching transistors during a program operation with respect to the memory block, wherein the boosting operation is performed based on the program operation being performed with respect to a second stack, and the boosting operation is omitted based on the program operation being performed with respect to a first stack. ### Claim 2 (depends on 1) The method of claim 1, wherein the performing the boosting operation comprises: applying a first pass voltage to wordlines of an erased stack among the stacks while the intermediate switching transistors are turned on, the erased stack indicating a stack in which all memory cells are in an erased state; after the first pass voltage is applied to the wordlines of the erased stack, applying a second pass voltage to wordlines of a selected stack among the stacks while the intermediate switching transistors are turned off, the selected stack indicating a stack which comprises memory cells to be programmed. ### Claim 3 (depends on 2) The method of claim 2, wherein the channels of the erased stack and the channels of the selected stack are electrically connected to each other by turning-on the intermediate switching transistors while the first pass voltage is applied to the wordlines of the erased stack, and wherein the channels of the erased stack and the channels of the selected stack are electrically disconnected from each other by turning-off of the intermediate switching transistors while the second pass voltage is applied to the wordlines of the selected stack. ### Claim 4 (depends on 2) The method of claim 2, wherein after the second pass voltage is applied to the wordlines of the selected stack, a voltage to which the channels of the selected stack are boosted is higher than a voltage to which the channels of the erased stack are boosted. ### Claim 5 (depends on 2) The method of claim 2, wherein the performing the boosting operation further comprises: before the first pass voltage is applied to the wordlines of the erased stack, applying a precharge voltage to the channels of the selected stack and the channels of the erased stack while the intermediate switching transistors are turned on. ### Claim 6 (depends on 2) The method of claim 2, further comprising: performing a recovery operation to initialize wordline voltages of the stacks by controlling the switching operation of the intermediate switching transistors, wherein the performing the recovery operation comprises: decreasing voltages of the wordlines of the selected stack from the second pass voltage to an intermediate voltage lower than the second pass voltage and higher than an initialization voltage; and turning on the intermediate switching transistors after the voltage of the wordlines of the selected stack are decreased to the intermediate voltage. ### Claim 7 (depends on 6) The method of claim 6, wherein the performing the recovery operation further comprises: decreasing voltages of the wordlines of the erased stack from the first pass voltage to the initialization voltage, and, at a substantially same time, decreasing the voltages of the wordlines of the selected stack from the intermediate voltage to the initialization voltage. ### Claim 8 (depends on 2) The method of claim 2, further comprising: controlling the boosting operation based on a program line number corresponding to a number of wordlines connected to memory cells previously programmed in the selected stack. ### Claim 9 (depends on 8) The method of claim 8, wherein the controlling the boosting operation comprises: performing the boosting operation based on the program line number being smaller than a reference number; and omitting the boosting operation based on the program line number being greater than the reference number. ### Claim 10 (depends on 8) The method of claim 8, wherein the controlling the boosting operation comprises: decreasing the first pass voltage as the program line number increases. ### Claim 11 (depends on 8) The method of claim 8, wherein the performing the boosting operation further comprises: before the first pass voltage is applied to the wordlines of the erased stack, applying a precharge voltage to the channels of the selected stack and the channels of the erased stack while the intermediate switching transistors are turned on, and wherein the controlling the boosting operation comprises: decreasing the precharge voltage as the program line number increases. ### Claim 12 (depends on 1) The method of claim 1, further comprising: performing a program scenario such that the program operation is performed in a downward direction from an uppermost wordline, wherein the stacks comprise the first stack below the boundary portion and the second stack above the boundary portion. ### Claim 13 (depends on 12) The method of claim 12, further comprising: applying a precharge voltage to the channels of the stacks through the source line before the boosting operation is performed. ### Claim 14 (depends on 1) The method of claim 1, further comprising: performing a program scenario such that the program operation is performed in an upward direction from a lowest wordline of the stacks, wherein the stacks comprise the first stack below the boundary portion and the second stack above the boundary portion. ### Claim 15 (depends on 14) The method of claim 14, further comprising: applying a precharge voltage to the channels of the stacks through the bitlines before the boosting operation is performed. ### Claim 16 (depends on 1) The method of claim 1, wherein the boundary portion comprises a lower boundary portion and an upper boundary portion, wherein the stacks comprise the first stack below the lower boundary portion, the second stack between the lower boundary portion and the upper boundary portion, and a third stack above the upper boundary portion, and wherein the intermediate switching transistors comprise a plurality of lower switching transistors disposed in the lower boundary portion and a plurality of upper switching transistors disposed in the upper boundary portion. ### Claim 17 A nonvolatile memory device comprising: a memory cell region including a first metal pad; a peripheral circuit region including a second metal pad, wherein the peripheral circuit region is vertically connected to the memory cell region by the first metal pad and the second metal pad; a memory block in the memory cell region, the memory block comprising a plurality of stacks disposed in a vertical direction, each memory block comprising a plurality of cell strings, each cell string comprising a plurality of memory cells connected in series in the vertical direction between a source line and each of a plurality of bitlines; a plurality of intermediate switching transistors disposed in a boundary portion between two adjacent stacks in the vertical direction, the intermediate switching transistors performing a switching operation to control electrical connection of the cell strings, respectively; and a control circuit in the peripheral circuit region, the control circuit configured to perform a boosting operation to boost voltages of channels of the stacks while controlling the switching operation of the intermediate switching transistors during a program operation with respect to the memory block, wherein the boosting operation is performed based on the program operation being performed with respect to a second stack, and the boosting operation is omitted based on the program operation being performed with respect to a first stack. ### Claim 18 (depends on 17) The nonvolatile memory device of claim 17, wherein the first metal pad and the second metal pad comprise copper. ### Claim 19 (depends on 17) The nonvolatile memory device of claim 17, wherein the first metal pad is bonded to the second metal pad. ### Claim 20 (depends on 17) The nonvolatile memory device of claim 17, wherein the memory cell region is formed on a first wafer and the peripheral circuit region is formed on a second wafer.