# US 2020/0401924 A1 · Modular, frequency-flexible, superconducting quantum processor architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401924 A1 - Document ID: US20200401924A1 - Status: Published application - Kind: A1 - Application number: 16/449,239 - Filed: 2019-06-21 - Published: 2020-12-24 - Earliest claimed: 2019-06-21 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Hanhee Paik; Jae-Woong Nah; Paul S. Andry; Martin O. Sandberg - Web page: https://patentgrep.com/patent/US20200401924A1 ## CPC - H10N 69/00: Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00 - H10N 60/00: Superconducting devices (integrated devices or assemblies of multiple devices H10N69/00) - H10W 70/668: {Superconducting materials} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/072: {of bump connectors} - H10W 72/07254: {changes in dispositions} - H10W 72/073: {of die-attach connectors} - H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/354: {comprising polymers} - H10W 72/9223: {with redistribution layers [RDL]} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A modular superconducting quantum processor includes a first superconducting chip including a first plurality of qubits each having substantially a first resonance frequency and a second plurality of qubits each having substantially a second resonance frequency, the first resonance frequency being different from the second resonance frequency, and a second superconducting chip including a third plurality of qubits each having substantially the first resonance frequency and a fourth plurality of qubits each having substantially the second resonance frequency. The quantum processor further includes an interposer chip connected to the first superconducting chip and to the second superconducting chip. The interposer chip has interposer coupler elements configured to couple the second plurality of qubits to the fourth plurality of qubits. ## Claims ### Claim 1 A modular superconducting quantum processor, comprising: a first superconducting chip comprising a first plurality of qubits each having substantially a first resonance frequency and a second plurality of qubits each having substantially a second resonance frequency, the first resonance frequency being different from the second resonance frequency; a second superconducting chip comprising a third plurality of qubits each having substantially the first resonance frequency and a fourth plurality of qubits each having substantially the second resonance frequency; and an interposer chip connected to said first superconducting chip and to said second superconducting chip, wherein the interposer chip comprises interposer coupler elements configured to couple the second plurality of qubits having substantially the second resonance frequency to the fourth plurality of qubits having substantially the second resonance frequency. ### Claim 2 (depends on 1) The modular superconducting quantum processor according to claim 1, wherein the second plurality of qubits are arranged at a periphery in the first superconducting chip and the fourth plurality of qubits are arranged at a periphery of the second superconducting chip so as to enable coupling between the second plurality of qubits and the fourth plurality of qubits. ### Claim 3 (depends on 1) The modular superconducting quantum processor according to claim 1, wherein the first superconducting chip further comprises a first plurality of coupling elements configured to couple the first plurality of qubits with the second plurality of qubits. ### Claim 4 (depends on 1) The modular superconducting quantum processor according to claim 1, wherein the second superconducting chip further comprises a second plurality of coupling elements configured to couple the third plurality of qubits with the fourth plurality of qubits. ### Claim 5 (depends on 1) The modular superconducting quantum processor according to claim 1, wherein the first superconducting chip and the second superconducting chip comprise readout elements to readout each of the first plurality of qubits, each of the second plurality of qubits, each of the third plurality of qubits or each of the fourth plurality of qubits or to readout any combination thereof. ### Claim 6 (depends on 1) The modular superconducting quantum processor according to claim 1, wherein the first superconducting chip and the second superconducting chip comprises ground elements configured to connect ground planes of the first superconducting chip and the second superconducting chip. ### Claim 7 (depends on 1) The modular superconducting quantum processor according to claim 1, wherein the interposer chip comprises ground elements configured to connect ground planes on the interposer chip. ### Claim 8 (depends on 1) The modular superconducting quantum processor according to claim 1, wherein the interposer coupler elements are selected from the group consisting of a resonator, a direct capacitive coupler, and a frequency tunable element. ### Claim 9 (depends on 1) The modular superconducting quantum processor according to claim 1, wherein the first plurality of qubits and the third plurality of qubits are arranged in frequency to implement cross-resonance (CR) gates. ### Claim 10 (depends on 1) The modular superconducting quantum processor according to claim 1, wherein the second plurality of qubits and the fourth plurality of qubits comprise tunable gates or resonance induced phase (RIP) gates. ### Claim 11 (depends on 1) The modular superconducting quantum processor according to claim 1, further comprising a substrate, wherein the first and second superconducting chips are mounted to the substrate and the first plurality of qubits, the second plurality of qubits, the third plurality of qubits, and the fourth plurality of qubits are connected to the substrate through a plurality of vias and solder bumps, wherein the plurality of vias are configured to input and output signals to the first, second, third and fourth plurality of qubits through the substrate. ### Claim 12 (depends on 11) The modular superconducting quantum processor according to claim 11, wherein the first and second superconducting chips are mounted to the substrate so as to allow free access to the first, second, third and fourth plurality of qubits from a side of the first and second superconducting chips that is opposite a side of the first and second superconducting chips facing the substrate. ### Claim 13 (depends on 11) The modular superconducting quantum processor according to claim 11, wherein the interposer chip is connected to the first and second superconducting chips and the substrate using solder bumps. ### Claim 14 (depends on 1) The modular superconducting quantum processor according to claim 1, wherein the first superconducting chip, the second superconducting chip, and the interposer chip are configured and arranged to provide a modular system so as to enable direct accessibility to each of the first, second, third and fourth qubits. ### Claim 15 (depends on 1) The modular superconducting quantum processor according to claim 1, further comprising: a plurality of first superconducting chips comprising the first plurality of qubits and the second plurality of qubits; a plurality of second superconducting chips comprising the third plurality of qubits and the fourth plurality of qubits, wherein the interposer chip is configured to connect to said plurality of first superconducting chips and to said plurality of second superconducting chips. ### Claim 16 A method of making a modular superconducting quantum processor, comprising: providing a first superconducting chip, the first superconducting chip comprising a first plurality of qubits each having substantially a first resonance frequency and a second plurality of qubits each having substantially a second resonance frequency, the first resonance frequency being different from the second resonance frequency; providing a second superconducting chip, the second superconducting chip comprising a third plurality of qubits each having substantially the first resonance frequency and a fourth plurality of qubits each having substantially the second resonance frequency; providing an interposer chip comprising interposer coupler elements configured to couple the second plurality of qubits having substantially the second resonance frequency to the fourth plurality of qubits having substantially the second resonance frequency; mounting the first superconducting chip and the second superconducting chip on a substrate; and mounting the interposer chip on at least a portion of the first superconducting chip, on at least a portion of the second superconducting chip, and on at least a portion of the substrate such that the first plurality of qubits, the second plurality of qubits, the third plurality of qubits and the fourth plurality of qubits are accessible from a side opposite to a side facing the substrate. ### Claim 17 (depends on 16) The method according to claim 16, further comprising conductively connecting the first plurality, the second plurality, the third plurality and the fourth plurality of qubits to the substrate and conductively connecting the interposer chip to the substrate and to the first superconducting chip and to the second superconducting chip. ### Claim 18 (depends on 16) The method according to claim 16, wherein mounting the first superconducting chip and the second superconducting chip on the substrate comprises connecting the first, the second, the third and fourth plurality of qubits to the substrate using a plurality of vias in the first and second superconducting chips and solder bumps, wherein the plurality of vias are configured to input and output signals to the first, second, third and fourth plurality of qubits through the substrate. ### Claim 19 (depends on 16) The method according to claim 16, further comprising producing the first plurality of qubits and the second plurality of qubits on a first substrate to form the first superconducting chip; and producing the third plurality of qubits and the fourth plurality of qubits on a second substrate to form the second superconducting chip. ### Claim 20 (depends on 19) The method according to claim 19, wherein producing the first plurality of qubits and the second plurality of qubits on the first substrate comprises producing the first plurality of qubits and the second plurality of qubits on a first non-conductive substrate, wherein producing the third plurality of qubits and the fourth plurality of qubits on the second substrate comprises producing the third plurality of qubits and the fourth plurality of qubits on a second non-conductive substrate. ### Claim 21 (depends on 19) The method according to claim 19, wherein producing the first plurality of qubits and the second plurality of qubits on the first substrate comprises producing the second plurality of qubits at a periphery in the first substrate, and wherein producing the third plurality of qubits and the fourth plurality of qubits on the second substrate comprises producing the fourth plurality of qubits at a periphery of the second substrate so as to enable conductive coupling between the second plurality of qubits and the fourth plurality of qubits. ### Claim 22 A quantum computer comprising a modular superconducting quantum processor, wherein the modular superconducting quantum processor comprises: a first superconducting chip comprising a first plurality of qubits each having substantially a first resonance frequency and a second plurality of qubits each having substantially a second resonance frequency, the first resonance frequency being different from the second resonance frequency; a second superconducting chip comprising a third plurality of qubits each having substantially the first resonance frequency and a fourth plurality of qubits each having substantially the second resonance frequency; and an interposer chip connected to said first superconducting chip and to said second superconducting chip, wherein the interposer chip comprises interposer coupler elements configured to couple the second plurality of qubits having substantially the second resonance frequency to the fourth plurality of qubits having substantially the second resonance frequency.