# US 2020/0401875 A1 · Integrated circuit chip apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401875 A1 - Document ID: US20200401875A1 - Status: Published application - Kind: A1 - Application number: 17/010,761 - Filed: 2020-09-02 - Published: 2020-12-24 - Earliest claimed: 2019-01-28 - Assignees: Cambricon Technologies Corporation Limited - Applicants: Cambricon Technologies Corporation Limited - Inventors: Shaoli Liu; Xinkai Song; Bingrui Wang; Yao Zhang; Shuai Hu - Web page: https://patentgrep.com/patent/US20200401875A1 ## CPC - G06N 3/063: using electronic means - G06F 7/483: Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 17/153: {Multidimensional correlation or convolution} - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06N 3/04: Architecture, e.g. interconnection topology - G06N 3/044: Recurrent networks, e.g. Hopfield networks - G06N 3/045: Combinations of networks - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/06: Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons - G06N 3/08: Learning methods - H10W 90/00: Package configurations - G06F 2207/4824: Neural networks - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated circuit chip apparatus and a processing method performed by an integrated circuit chip apparatus are disclosed. The disclosed integrated circuit chip apparatus and processing method are used for executing a multiplication operation, a convolution operation, or a training operation of a neural network. The present technical solution has the advantages of a reduced computational cost and low power consumption. ## Claims ### Claim 1 An integrated circuit chip apparatus, comprising: a main processing circuit and a plurality of basic processing circuits, wherein the main processing circuit comprises a data type conversion circuit configured to convert data between a floating point data type and a fixed point data type; wherein the main processing circuit is configured to: receive an input data block, a weight data block, and a multiplication instruction; convert the input data block and the weight data block to an input data block of the fixed point type and a weight data block of the fixed point type, respectively, using the data type conversion circuit; designate the input data block of the fixed point type as a distribution data block and the weight data block of the fixed point type as a broadcasting data block according to the multiplication instruction; partition the distribution data block to obtain a plurality of basic data blocks; distribute the plurality of basic data blocks to at least one of the plurality of basic processing circuits; and broadcast the broadcasting data block to the plurality of basic processing circuits; wherein the at least one of the plurality of basic processing circuits is configured to perform computations on the broadcasting data block and the received basic data blocks according to the fixed point type to obtain computation results, and transfer the computation results to the main processing circuit; wherein the main processing circuit is configured to process the computation results to obtain an instruction result of the multiplication instruction. ### Claim 2 (depends on 1) The integrated circuit chip apparatus of claim 1, wherein the input data block is a vector or a matrix; ### Claim 3 (depends on 1) The integrated circuit chip apparatus of claim 1, wherein the weight data block is a vector or a matrix. ### Claim 4 (depends on 1) The integrated circuit chip apparatus of claim 1, wherein: the at least one of the plurality of basic processing circuits is configured to perform multiplication on the broadcasting data block and the received basic data blocks according to the fixed point type to obtain products of the fixed point type, and transfer the products as computation results to the main processing circuit, the main processing circuit is configured to convert the products of the fixed point type to products of the floating point type using the data type conversion circuit, accumulate the products of the floating point type to obtain accumulation results, and sort the accumulation results to obtain the instruction result. ### Claim 5 (depends on 1) The integrated circuit chip apparatus of claim 1, wherein: the at least one of the plurality of basic processing circuits is configured to perform inner product computations on the broadcasting data block and the received basic data blocks according to the fixed point type to obtain inner products of the fixed point type, and transfer the inner products as computation results to the main processing circuit, the main processing circuit is configured to convert the inner products of the fixed point type to inner products of the floating point type using the data type conversion circuit, and sort the inner products to obtain the instruction result. ### Claim 6 (depends on 1) The integrated circuit chip apparatus of claim 1, further comprising a branch processing circuit, wherein the branch processing circuit is located between the main processing circuit and at least one basic processing circuit, wherein the branch processing circuit is configured to forward data between the main processing circuit and at least one basic processing circuit. ### Claim 7 (depends on 1) The integrated circuit chip apparatus of claim 1, wherein the main processing circuit is configured to broadcast the broadcasting data block as a whole to the plurality of basic processing circuits. ### Claim 8 (depends on 1) The integrated circuit chip apparatus of claim 1, wherein the main processing circuit is further configured to partition the broadcasting data block into a plurality of partial broadcasting data blocks, and sequentially broadcast the plurality of partial broadcasting data blocks to the plurality of basic processing circuits. ### Claim 9 (depends on 8) The integrated circuit chip apparatus of claim 8, wherein the at least one of the plurality of basic processing circuits is configured to sequentially perform inner product processing on the partial broadcasting data blocks and the basic data blocks according to the fixed point type to obtain results of inner product processing, and transfer the results of inner product processing to the main processing circuit. ### Claim 10 (depends on 9) The integrated circuit chip apparatus of claim 9, wherein the at least one of the plurality of basic processing circuits is configured to reuse each partial broadcasting data block for n times to perform inner product computations on the partial broadcasting data blocks and n basic data blocks respectively to obtain n partial processing results, and transfer the n partial processing results to the main processing circuit, wherein n is an integer greater than or equal to 2. ### Claim 11 (depends on 1) The integrated circuit chip apparatus of claim 1, wherein the multiplication instruction is for performing a matrix-multiply-vector computation, and the main processing circuit is further configured to transfer data of at least one row of a matrix to a basic processing circuit at a time. ### Claim 12 A processing method performed by an integrated circuit chip apparatus that comprises a main processing circuit and a plurality of basic processing circuits, wherein the main processing circuit comprises a data type conversion circuit configured to convert data between a floating point data type and a fixed point data type, wherein the processing method comprises: receiving an input data block, a weight data block, and a multiplication instruction; converting, by the data type conversion circuit, the input data block and the weight data block to an input data block of the fixed point type and a weight data block of the fixed point type, respectively; designating the input data block of the fixed point type as a distribution data block and the weight data block of the fixed point type as a broadcasting data block according to the multiplication instruction; partitioning, by the main processing unit, the distribution data block to obtain a plurality of basic data blocks; distributing, by the main processing circuit, the plurality of basic data blocks to at least one of the plurality of basic processing circuits; broadcasting, by the main processing circuit, the broadcasting data block to the plurality of basic processing circuits; performing computations, by the at least one of the plurality of basic processing circuits, on the broadcasting data block and the received basic data blocks according to the fixed point type to obtain computation results; transfer, by the at least one of the plurality of basic processing circuits, the computation results to the main processing circuit; and processing, by the main processing circuit, the computation results to obtain an instruction result of the multiplication instruction. ### Claim 13 (depends on 12) The processing method of claim 12, wherein the input data block is a vector or a matrix and the weight data block is a vector or a matrix. ### Claim 14 (depends on 12) The processing method of claim 12, further comprising: performing, by the at least one of the plurality of basic processing circuits, multiplication on the broadcasting data block and the received basic data blocks according to the fixed point type to obtain products of the fixed point type; transferring, by the at least one of the plurality of basic processing circuits, the products as computation results to the main processing circuit; converting the products of the fixed point type to products of the floating point type using the data type conversion circuit; accumulate, by the main processing circuit, the products of the floating point type to obtain accumulation results; and sorting the accumulation results to obtain the instruction result. ### Claim 15 (depends on 12) The processing method of claim 12, further comprising: performing, by the at least one of the plurality of basic processing circuits, inner product computations on the broadcasting data block and the received basic data blocks according to the fixed point type to obtain inner products of the fixed point type; transferring, by the at least one of the plurality of basic processing circuits, the inner products as computation results to the main processing circuit; converting the inner products of the fixed point type to inner products of the floating point type using the data type conversion circuit; and sorting the inner products to obtain the instruction result. ### Claim 16 (depends on 12) The processing method of claim 12, further comprising: partitioning the broadcasting data block into a plurality of partial broadcasting data blocks; and sequentially broadcasting, by the main processing circuit, the plurality of partial broadcasting data blocks to the plurality of basic processing circuits. ### Claim 17 (depends on 16) The processing method of claim 16, further comprising: sequentially performing, by the at least one of the plurality of basic processing circuits, inner product processing on the partial broadcasting data blocks and the basic data blocks according to the fixed point type to obtain results of inner product processing; and transferring, by the at least one of the plurality of basic processing circuits, the results of inner product processing to the main processing circuit. ### Claim 18 (depends on 12) The processing method of claim 12, wherein the multiplication instruction is for performing a matrix-multiply-vector computation, and the processing method further comprises: transferring, by the main processing circuit, data of at least one row of a matrix to a basic processing circuit at a time. ### Claim 19 A neural network computation device, comprising one or more integrated circuit chip apparatuses, each integrated circuit chip apparatus comprising: a main processing circuit and a plurality of basic processing circuits, wherein the main processing circuit comprises a data type conversion circuit configured to convert data between a floating point data type and a fixed point data type; wherein the main processing circuit is configured to: receive an input data block, a weight data block, and a multiplication instruction; convert the input data block and the weight data block to an input data block of the fixed point type and a weight data block of the fixed point type, respectively, using the data type conversion circuit; designate the input data block of the fixed point type as a distribution data block and the weight data block of the fixed point type as a broadcasting data block according to the multiplication instruction; partition the distribution data block to obtain a plurality of basic data blocks; distribute the plurality of basic data blocks to at least one of the plurality of basic processing circuits; and broadcast the broadcasting data block to the plurality of basic processing circuits; wherein the at least one of the plurality of basic processing circuits is configured to perform computations on the broadcasting data block and the received basic data blocks according to the fixed point type to obtain computation results, and transfer the computation results to the main processing circuit; wherein the main processing circuit is configured to process the computation results to obtain an instruction result of the multiplication instruction. ### Claim 20 (depends on 19) The neural network computation device of claim 19, wherein: the at least one of the plurality of basic processing circuits is configured to perform multiplication on the broadcasting data block and the received basic data blocks according to the fixed point type to obtain products of the fixed point type, and transfer the products as computation results to the main processing circuit, the main processing circuit is configured to convert the products of the fixed point type to products of the floating point type using the data type conversion circuit, accumulate the products of the floating point type to obtain accumulation results, and sort the accumulation results to obtain the instruction result.