# US 2020/0401730 A1 · A secure software-defined radio chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401730 A1 - Document ID: US20200401730A1 - Status: Published application - Kind: A1 - Application number: 16/956,618 - Filed: 2018-11-28 - Published: 2020-12-24 - Earliest claimed: 2017-12-22 - Assignees: Nagravision Sarl - Applicants: Nagravision SA - Inventors: Joël M. CONUS - Web page: https://patentgrep.com/patent/US20200401730A1 ## CPC - G06F 21/72: in cryptographic circuits - H04L 63/123: {received data contents, e.g. message integrity} - G06F 9/44505: {Configuring for program initiating, e.g. using registry, configuration files} - G06F 21/57: Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities - G06F 21/76: in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] - H04B 1/0003: {Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain (digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00)} - H04B 1/0014: {using DSP [Digital Signal Processor] quadrature modulation and demodulation} - H04W 12/10: Integrity - H04W 12/35: {Protecting application or service provisioning, e.g. securing SIM application provisioning} - G06F 2221/033: Test or assess software - H04L 63/0435: {wherein the sending and receiving network entities apply symmetric encryption, i.e. same key used for encryption and decryption (cryptographic mechanisms or cryptographic arrangements for symmetric key encryption H04L9/06)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H04B: TRANSMISSION - H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72) ## Abstract The present invention relates to a software-defined radio chip or module suitable for integration on a host device. The software-defined radio chip comprises digital signal processing capability which includes standard digital signal processing hardware and reconfigurable programmable logic, the reconfigurable programmable logic is configured in such a way as to provide secure digital signal processing capability to the software-defined radio, thereby providing a secure software-defined radio. ## Claims ### Claim 1 A software-defined radio chip comprising: a digital front end for converting digital intermediate frequency samples to digital baseband samples; and a digital back end for processing the digital baseband samples to provide a consumable content; the software-defined radio chip further comprising a reconfigurable hardware programmable logic circuit configured at least to function as the digital front end; characterised in that the reconfigurable hardware programmable logic circuit comprises a secure cryptographic device for providing a root of trust having a particular key as part of a key ladder scheme. ### Claim 2 (depends on 1) The software-defined radio chip according to claim 1, wherein the digital back end comprises a digital signal processing module. ### Claim 3 (depends on 1) The software-defined radio chip according to claim 1, wherein the reconfigurable hardware programmable logic circuit is further configured to function as the digital back end. ### Claim 4 The software-defined radio chip according to any of the preceding claims, further comprising an analogue front end at least for converting a radio frequency signal to an analogue intermediate frequency signal and for converting the analogue intermediate frequency signal to provide the digital intermediate frequency samples. ### Claim 5 The software-defined radio chip according to any of the preceding claims, wherein the secure cryptographic device comprises: a configuration module comprising: a decrypt and verify module for decrypting and authenticating and/or verifying the integrity of configuration data; and a processing module for processing at least a portion of the configuration data; at least one cryptographic module accessible via at least one input/output module; and an interconnection network passing between modules of the secure cryptographic device; wherein the configuration module is arranged to configure at least one of the input/output module or cryptographic modules and/or at least a subset of the interconnect network. ### Claim 6 (depends on 5) The software-defined radio chip according to claim 5, wherein the processing module comprises a one-way function that is operable on the configuration data to provide processed configuration data. ### Claim 7 (depends on 5, 6) The software-defined radio chip according to either of claim 5 or 6, the system configured to perform the processing after the decryption and/or verification. ### Claim 8 (depends on 5, 6) The software-defined radio chip according to either of claim 5 or 6, the system configured to perform the processing before the decryption and/or the verification. ### Claim 9 (depends on 5, 6, 7, 8) The software-defined radio chip according to any of claims 5 to 8, in which it is arranged for the processed configuration data to be used to configure at least one of the input/output module or the cryptographic module. ### Claim 10 (depends on 5, 6, 7, 8, 9) The software-defined radio chip according to any of claims 5 to 9, wherein the input/output module or the cryptographic module comprises at least one of: a substitution box module, a substitution table module, a bit permutation module, a byte permutation module, or a matrix multiplication module. ### Claim 11 (depends on 10) The software-defined radio chip according to claim 10, the input/output module or the cryptographic module further comprising a hardener for a true random number generator or a physically un-clonable function, and/or a flexible state-machine, or a portion of the interconnection network. ### Claim 12 (depends on 4, 5, 6, 7, 8, 9, 10, 11) A system comprising: a software-defined radio chip according to any of claims 4 to 11; an antenna for receiving the radio frequency signal for the radio frequency signal; and a server for sending information to and/or receiving information from the software-defined radio chip, the server being configured to authenticate at least part of the information coming from the software-defined radio chip and the software-defined radio chip being configured to authenticate at least part of the information coming from the server. ### Claim 13 A method for programming a software-defined radio chip comprising a reconfigurable hardware programmable logic circuit, the software-defined radio chip comprising a root of trust, the method comprising: loading information onto the reconfigurable hardware programmable logic circuit after authenticating and decrypting the information using a key as part of a key ladder derived from particular key of the root of trust. ### Claim 14 (depends on 13) The method according to claim 13, further comprising: loading configuration data onto the reconfigurable hardware programmable logic circuit; processing at least a portion of the configuration data via a one-way function to form processed configuration data; and configuring at least one configurable module of the reconfigurable hardware programmable logic circuit using the processed configuration data. ### Claim 15 (depends on 14) The method according to claim 14, further comprising deciphering the configuration data and/or wherein the loading step comprises verifying the authenticity and/or integrity of the configuration data using either an asymmetric key or a symmetric key. ### Claim 16 (depends on 14, 15) The method according to either of claim 14 or 15, wherein the configuring step comprises at least one of: initialising the reconfigurable hardware programmable logic circuit; configuring a configurable module of the reconfigurable hardware programmable logic circuit; and configuring an interconnection between modules of the reconfigurable hardware programmable logic circuit wherein the modules may be configurable or non-configurable.