# US 2020/0401691 A1 · System and method for active cyberattack defense > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401691 A1 - Document ID: US20200401691A1 - Status: Published application - Kind: A1 - Application number: 16/907,050 - Filed: 2020-06-19 - Published: 2020-12-24 - Earliest claimed: 2019-06-19 - Assignees: Arizona Board of Regents On Behalf of Northern Arizona University - Applicants: Arizona Board of Regents on Behalf of Northern Arizona University - Inventors: Paul G. Flikkema; Bertrand F. Cambou; James D. Palmer - Web page: https://patentgrep.com/patent/US20200401691A1 ## CPC - G06F 21/52: during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} - G06F 21/57: Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities - G06F 21/125: {by manipulating the program code, e.g. source code, compiled code, interpreted code, machine code} - G06F 21/1062: {Editing} - G06F 2221/033: Test or assess software - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Computing systems with dynamic architectures may be used to secure against code-injection attacks and other exploits. A system may generate multiple representations of instructions or other data associated with each of a set of configurations of the system. The system may periodically or randomly change configurations such that malicious code that is executable in one configuration cannot be executed in another configuration. A system may also detect malicious code by comparing code previously generated in one representation with different representations of the same code. If, during execution of a representation of a program code, the system determines that the representation specifies instructions that differ from other representations of the same program code, they system may stop executing the compromised program code, change its configuration, and continue to execute another representation of the program code that has not been compromised. ## Claims ### Claim 1 A computing system, comprising: a processor configured to process machine code instructions specified according to at least two machine code instruction formats, the processor including configuration management circuitry configured to control a machine code configuration of the processor; and memory coupled to the processor; wherein the configuration management circuitry is configured to cause the processor to: accept, at a first time, instructions specified according to a first machine code instruction format and reject instructions specified according to a second machine code instruction format; accept, at a second time, instructions specified according to the second machine code instruction format and reject instructions specified according to the first machine code instruction format; and wherein the computing system is configured to: receive first machine code specifying first program code according to the first machine code instruction format; generate second machine code specifying the first program code according to the second machine code instruction format and store the second machine code in the memory; determine, in response to a first request to execute the first machine code, that the first machine code corresponds to a set of processor operations equivalent to the second machine code; and execute the first machine code. ### Claim 2 (depends on 1) The computing system of claim 1, wherein the computing system is further configured to: determine, in response to a second request to execute the first machine code, that the first machine code does not correspond to a set of processor operations equivalent to the second machine code; and prevent execution of the first machine code. ### Claim 3 (depends on 2) The computing system of claim 2, wherein the configuration circuitry is further configured to: receive a signal indicating that the first machine code does not specify a set of processor operations equivalent to the second machine code; and reconfigure the processor, in response to receiving that signal, to reject instructions specified according to the first machine code instruction format and accept instructions specified according to the second machine code instruction format. ### Claim 4 (depends on 2) The computing system of claim 2 wherein the computing system is further configured to: identify a foreign instruction in the first machine code having no equivalent instructions in the second machine code; cease execution of the first machine code at a first location before execution of the foreign instruction; and begin execution of the second machine code at a location in the second machine code equivalent to the first location. ### Claim 5 (depends on 3) The computing system of claim 3, wherein the configuration circuitry is further configured to: generate third machine code specifying first program code according to the first machine code instruction format by translating the second machine code according to the first machine code instruction format and storing the third machine code in the memory in place of the first machine code. ### Claim 6 (depends on 1) The computing system of claim 1, wherein: when the processor is configured to accept instructions specified according to the first machine code instruction format, the configuration circuitry is configured to: reconfigure the processor, in response to receiving a security signal, to reject instructions specified according to the first machine code instruction format and accept instructions specified according to the second machine code instruction format; and when the processor is configured to accept instructions specified according to the second machine code instruction format, the configuration circuitry is configured to: reconfigure the processor, in response to receiving the security signal, to reject instructions specified according to the second machine code instruction format and accept instructions specified according to the first machine code instruction format; and ### Claim 7 (depends on 6) The computing system of claim 6, wherein the signal security signal indicates an attempted code injection attack directed toward to the computing system. ### Claim 8 (depends on 6) The computing system of claim 6, wherein system is configured to repeatedly generate the security signal at either of a random interval and a predetermined interval. ### Claim 9 (depends on 1) The computing system of claim 1 wherein the computing system is further configured to: generate the second machine code while executing the first machine code. determine, in response to a first request to execute the first machine code, that the first machine code specifies an identical set of processor operations as the second machine code; and execute the first machine code. ### Claim 10 A computing system, comprising: a processor, memory coupled to the processor, and a configuration controller configured to receive and process instructions directed to the computing system, the configuration controller further configured to: cause the computing system to implement a first machine architecture at a first time; and cause the computing system to implement a second machine architecture at a second time; wherein, the computing system is configured, at the first time, to execute machine code instructions configured for execution by the computing system while implementing the first machine architecture and reject machine code instructions configured for execution by computing system while implementing the second machine architecture; wherein, the computing system is configured, at the second time, to execute machine code instructions configured for execution by the computing system while implementing the second machine architecture and reject machine code instructions configured for execution by the computing system while implementing the first machine architecture; and wherein the configuration controller is further configured to respond to a configuration signal by reconfiguring the computing system to implement either of the first machine architecture and the second machine architecture. ### Claim 11 (depends on 10) The computing system of claim 10, wherein: when the computing system implements the first machine architecture, the processor is configured to allow computing processes to access a first set of memory addresses and to prevent access to a second set of memory addresses; and when the computing system implements the second machine architecture, the processor is configured to allow computing processes to access the second set of memory addressees and to exclude access to the first set of memory addresses. ### Claim 12 (depends on 11) The computing system of claim 11, wherein the computing system: stores data accessible by the processor at the first set of memory addresses in a positional notation having a first radix; and stores data accessible by the processor at the second set of memory addresses in a positional notation having a second radix different from the first radix. ### Claim 13 (depends on 10) The computing system of claim 10, wherein the configuration controller is configured to: receive the machine code instructions configured for execution by the computing system while implementing the first machine architecture specified in a digital encoding using a first radix; and receive the machine code instructions configured for execution by the computing system while implementing the second machine architecture specified in a digital encoding using a second radix different than the first radix. ### Claim 14 (depends on 13) The computing system of claim 13, wherein the processor comprises: a first execution unit having circuitry configured to receive input signals and generate output signals having a number of possible states corresponding to a number of unique values in the first radix; and a second execution unit having circuitry configured to receive input signals and generate output signals having a number of possible states corresponding to a number of unique values in the first second radix; and wherein the configuration controller is configured to: transmit the machine code instructions configured for execution by the computing system while implementing the first machine architecture to the first execution unit; and transmit the machine code instructions configured for execution by the computing system while implementing the second machine architecture to the second execution unit. ### Claim 15 A computer-implemented method, comprising: receiving, by reconfigurable processing circuitry operating in a first configuration, first program code executable by the processing circuitry in the first configuration; transforming the first program code into an alternate representation and storing it in memory coupled to the processing circuitry as second program code that is executable by the processing circuitry in a second configuration and not executable in the first configuration; receiving a request to execute the first program code; determining that a first set of processing operations as described by the first program code differs from a second set of processing operations as described by the second program code; and suspending operations of the processing circuitry in response to determining that the first and second sets of processing operations are different. ### Claim 16 (depends on 15) The method of claim 15, further comprising: reconfiguring the processing circuitry to operate in a second configuration in which the second program code is executable and the first program code is not executable; resuming operations of the processing circuitry in the second configuration; and executing the second program code in place of the first program code. ### Claim 17 (depends on 15) The method of claim 15, wherein transforming the first program code into the alternate representation comprises at least one of: reordering instructions of the first program in a modified order and configuring the processing circuitry to store the reordered instructions according to the modified order; altering memory location references in the first program code to refer to alternate memory locations; and encoding references to processing operations in the first program code using an alternate encoding that produces references to invalid processing operations according to the first configuration; ### Claim 18 (depends on 15) The method of claim 15, wherein transforming the first program code into the alternate representation comprises: encrypting the first program code using an encryption key to generate encrypted program code that cannot be executed when the processing circuitry is operated in the first configuration. ### Claim 19 (depends on 15) The method of claim 15, wherein transforming the first program code into the alternate representation comprises: translating instructions of the first program code specified according to a first machine language instruction set into instructions specified according to a second machine language instruction set. ### Claim 20 (depends on 19) The method of claim 19, wherein: the first machine language instruction set specifies input signals and output signals having a number of possible states corresponding to a number of unique values in a first positional notation having a first radix; and the second machine language instruction set specifies input signals and output signals having a number of possible states corresponding to a number of unique values in a second positional notation having a second radix different from the first radix.