# US 2020/0401673 A1 · Hierarchical clock tree implementation

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- Number: US 2020/0401673 A1
- Document ID: US20200401673A1
- Status: Published application
- Kind: A1
- Application number: 16/666,389
- Filed: 2019-10-28
- Published: 2020-12-24
- Earliest claimed: 2019-06-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hongda LU; Sridhar SUBRAMANIAM; Kok-Hoong CHIU
- Web page: https://patentgrep.com/patent/US20200401673A1

## CPC

- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 30/396: Clock trees
- G06F 2119/12: Timing analysis or timing optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of constructing a hierarchical clock tree for an integrated circuit may include constructing a clock distribution network on a first level, pushing the clock distribution network to a second level, implementing partition clock trees in partitions on the second level, and calculating combined timing of the clock distribution network and the partition clock trees on the second level. Implementing the partition clock trees may include constructing the partition clock trees in the partitions on the second level, calculating trial timing for the partition clock trees, calculating target timing constraints for the partition clock trees based on timing of the clock distribution network and the trial timing for the partition clock trees, and adjusting the timing of one or more of the partition clock trees based on the target constraints.

## Claims

### Claim 1

A method of constructing a hierarchical clock tree for an integrated circuit, the method comprising:
constructing a clock distribution network on a first level;
pushing the clock distribution network to a second level;
implementing partition clock trees in partitions on the second level; and
calculating combined timing of the clock distribution network and the partition clock trees on the second level.

### Claim 2 (depends on 1)

The method of claim 1, wherein implementing the partition clock trees comprises:
constructing the partition clock trees in the partitions on the second level;
calculating trial timing for the partition clock trees;
calculating target timing constraints for the partition clock trees based on timing of the clock distribution network and the trial timing for the partition clock trees; and
adjusting the timing of one or more of the partition clock trees based on the target timing constraints.

### Claim 3 (depends on 1)

The method of claim 1, wherein calculating the combined timing of the clock distribution network and the partition clock trees on the second level comprises merging the partition clock trees.

### Claim 4 (depends on 1)

The method of claim 1, further comprising adjusting the timing of one or more of the partition clock trees on the second level.

### Claim 5 (depends on 4)

The method of claim 4, wherein the timing of one or more of the partition clock trees on the second level is adjusted through engineering change orders (ECO).

### Claim 6 (depends on 4)

The method of claim 4, wherein the timing of one or more of the partition clock trees is adjusted by adjusting one or more target constraints for the one or more of the partition clock trees on the second level.

### Claim 7 (depends on 4)

The method of claim 4, further comprising:
determining that timing goals are not met by adjusting the timing of one or more of the partition clock trees; and
adjusting the clock tree distribution network.

### Claim 8 (depends on 1)

The method of claim 1 further comprising balancing the clock distribution network in parallel with balancing one or more of the partition clock trees.

### Claim 9

(canceled)

### Claim 10 (depends on 1)

The method of claim 1, wherein the clock distribution network is pushed into one or more of the partitions on the second level.

### Claim 11

(canceled)

### Claim 12

(canceled)

### Claim 13

A method of constructing a hierarchical clock tree for an integrated circuit, the method comprising:
constructing a clock distribution network at a first level;
pushing the clock distribution network to partitions at a second level;
calculating trial timing for the partitions at the second level;
calculating combined timing of the clock distribution network and the trial timing for the partitions at the second level;
calculating partition-level target constraints based on the combined timing of the clock distribution network and the trial timing for the partitions at the second level; and
calculating revised timing at the partition level based on the target constraints.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
merging the partitions at the partition level;
calculating revised combined timing of the clock distribution network and the revised timing for the partitions at the second level; and
checking if the revised combined timing meets design goals.

### Claim 15 (depends on 14)

The method of claim 14, further comprising balancing the hierarchical clock tree by adjusting the revised timing for the partitions at the second level.

### Claim 16 (depends on 15)

The method of claim 15, wherein the timing at the second level is adjusted through engineering change orders (ECO).

### Claim 17 (depends on 15)

The method of claim 15, wherein the timing at the second level is adjusted by adjusting the target constraints at the second level.

### Claim 18 (depends on 13)

The method of claim 13, wherein the timing comprises latency.

### Claim 19 (depends on 13)

The method of claim 13, wherein the timing comprises skew.

### Claim 20 (depends on 13)

The method of claim 13, wherein the partitions comprise abutted blocks.

### Claim 21

(canceled)

### Claim 22 (depends on 13)

The method of claim 13, wherein the partitions comprise multiple instantiated modules (MIMs).

### Claim 23 (depends on 13)

The method of claim 13, wherein a dependency between the clock distribution network and the partitions on the second level is decoupled.

### Claim 24

(canceled)

### Claim 25

A method of constructing a hierarchical clock tree for an integrated circuit, the method comprising:
constructing a top-level clock distribution network;
calculating distribution delays to endpoints of the clock distribution network;
pushing the top-level clock distribution network down to a block level;
constructing clock trees in blocks at the endpoints;
calculating block-level insertion delays for the clock trees in blocks at the endpoints;
combining the distribution delays with the block-level insertion delays to calculate clock tree insertion delays from a root of the top-level clock distribution network;
calculating delay target constraints for the blocks based on the clock tree insertion delays from the root of the top-level clock distribution network;
re-calculating block-level insertion delays based on the delay target constraints;
merging the clock trees at the block level; and
re-calculating the clock tree insertion delays from the root of the top-level clock distribution network.

### Claim at position 26

26-32. (canceled)