# US 2020/0401552 A1 · Methods and system for an integrated circuit

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- Number: US 2020/0401552 A1
- Document ID: US20200401552A1
- Status: Published application
- Kind: A1
- Application number: 16/947,050
- Filed: 2020-07-16
- Published: 2020-12-24
- Earliest claimed: 2019-06-20
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Yukihito TAKEDA; Tomonori KAMIYA
- Web page: https://patentgrep.com/patent/US20200401552A1

## CPC

- G06F 15/7864: {on more than one IC chip}
- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G06F 9/35: Indirect addressing
- G06F 9/3869: {Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking}
- G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals}
- G11C 7/1087: {Data input latches}
- G11C 7/109: {Control signal input circuits}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 8/20: Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Various embodiments of the present technology may provide methods and system for an integrated circuit. The system may provide a plurality of integrated circuits (i.e., slave devices) connected to and configured to communicate with a host device. Each integrated circuit may comprise a register storing a common default address. Each integrated circuit may further comprise an interface circuit configured to overwrite the default address of one integrated circuit with a new address while preventing changes to the remaining integrated circuits.

## Claims

### Claim 1

An integrated circuit, comprising:
a first input terminal adapted to receive an input data signal;
a second input terminal adapted to receive a clock signal;
a counter circuit adapted to generate a count value according to an oscillator;
an interface circuit connected to the first and second input terminals, and configured to generate a write protect signal according to the count value; and
a register in communication with the interface circuit and adapted to:
store an address; and
receive the write protect signal, wherein the write protect signal prevents changes to the address.

### Claim 2 (depends on 1)

The integrated circuit according to claim 1, wherein the interface circuit comprises: a compare circuit and a plurality of flip-flop circuits; wherein the compare circuit and the flip-flop circuits are adapted to operate together to generate the write protect signal.

### Claim 3 (depends on 2)

The integrated circuit according to claim 2, wherein the compare circuit is adapted to generate the write protect signal according to the input data signal and the output signal.

### Claim 4 (depends on 1)

The integrated circuit according to claim 1, wherein the interface circuit comprises:
a first flip-flop circuit, from the plurality of flip-flop circuits, connected to the first input terminal and adapted to receive the input data signal; and
a second flip-flop circuit, from the plurality of flip-flop circuits, connected to the second input terminal and adapted to generate an output signal.

### Claim 5 (depends on 1)

The integrated circuit according to claim 1, wherein the write protect signal comprises a high value and a low value.

### Claim 6 (depends on 5)

The integrated circuit according to claim 5, wherein the write protect signal prevents changes to the address when:
the output signal is a high value;
the input data signal is a low value; and
the write protect signal is the high value.

### Claim 7 (depends on 1)

The integrated circuit according to claim 1, further comprising a non-volatile memory in communication with the register.

### Claim 8 (depends on 1)

The integrated circuit according to claim 1, wherein the address of the register comprises one of a default address or a new address.

### Claim 9 (depends on 8)

The integrated circuit according to claim 8, wherein the interface is adapted to change the address of the register from the default address to the new address.

### Claim 10

A method for assigning addresses to plurality of slave devices connected to a host device, comprising:
transmitting a first communication signal to each slave device using a default address;
receiving a first acknowledgment signal from each slave device;
detecting one of the slave devices as having a first counter value that is the lowest-magnitude counter value relative to first counter values of the remaining slave devices; and
writing a first new address to the slave device associated with the first counter value having the lowest-magnitude counter value.

### Claim 11 (depends on 10)

The method according to claim 10, further comprising:
transmitting a second communication signal to each slave device using the default address;
receiving a second acknowledgment signal from at least two slave devices;
detecting one of the slave devices as having a second counter value that is the lowest-magnitude counter value relative to second counter values of the remaining slave devices; and
writing a second new address to the slave device associated with the second counter having the lowest-magnitude counter value.

### Claim 12 (depends on 10)

The method according to claim 10, further comprising receiving a non-acknowledgment signal from at least one of the slave devices.

### Claim 13

A system, comprising:
a host device; and
a plurality of integrated circuits connected to the host device via a common bus, wherein each integrated circuit comprises a first input terminal adapted to receive a data signal and a second input terminal adapted to receive a clock signal, and wherein each integrated circuit is configured to:
communicate with the host using a stored address, wherein the stored address is one of a default address or a new address;
generate a count value; and
generate a write protect signal according to the count value;
wherein the host device is adapted to write the new address to one of the integrated circuits based on the generated count value.

### Claim 14 (depends on 13)

The system according to claim 13, wherein each integrated circuit comprises:
a counter circuit adapted to generate the count value according to an oscillator;
an interface circuit connected to the first and second input terminals, and configured to generate a write protect signal according to the count value; and
a register in communication with the interface circuit and adapted to:
store the stored address.

### Claim 15 (depends on 14)

The system according to claim 14, wherein the interface circuit comprises:
a first flip-flop circuit connected to the first input terminal and adapted to receive the data signal; and
a second flip-flop circuit connected to the second input terminal and adapted to generate an output signal.

### Claim 16 (depends on 15)

The system according to claim 15, wherein the interface circuit further comprises a compare circuit connected to the first and second flip-flop circuits, wherein the compare circuit is adapted to generate the write protect signal according to the input signal and the output signal.

### Claim 17 (depends on 16)

The system according to claim 16, wherein the write protect signal prevents changes to the address when:
the output signal is a high value;
the input signal is a low value; and
the write protect signal is the high value.

### Claim 18 (depends on 14)

The system according to claim 14, wherein the write protect signal allows changes to the stored address of one of the integrated circuits and prevents changes to the stored address of the remaining integrated circuits.

### Claim 19 (depends on 13)

The system according to claim 13, wherein the host device is further adapted to:
transmit a first communication signal to each integrated circuit using a default address;
receive a first acknowledgment signal from each integrated circuit;
detect a first lowest-magnitude count value; and
write a first new address to the integrated circuit associated with the lowest-magnitude count value.

### Claim 20 (depends on 19)

The system according to claim 19, wherein the host device is further adapted to:
transmit a second communication signal to each integrated circuit using the default address;
receive a second acknowledgment signal from at least two integrated circuits;
detect a second lowest-magnitude count value; and
write a second new address to the integrated circuit associated with the lowest-magnitude count value.