# US 2020/0401550 A1 · Autonomous memory architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401550 A1 - Document ID: US20200401550A1 - Status: Published application - Kind: A1 - Application number: 17/011,686 - Filed: 2020-09-03 - Published: 2020-12-24 - Earliest claimed: 2009-09-11 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology Inc. - Inventors: Sean Eilert; Mark Leinwander; Jared Hulbert - Web page: https://patentgrep.com/patent/US20200401550A1 ## CPC - G06F 15/17318: {Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass configuration routing information and initiate instructions to disperse portions of the database to neighboring die using an interface that handles inter-die communication. Information is then extracted from the pool of autonomous memory and passed through a host interface to the host controller. ## Claims ### Claim 1 A system comprising: a host interface to communicate with a host device; and a distributed array of autonomous memory devices implemented by a plurality of die, the distributed array being configured to communicate with the host device by the host interface, a single die of the plurality of die comprising an individual autonomous memory device of the distributed array, the individual autonomous memory device comprising a microcontroller to perform computations independently of the host device, the individual autonomous memory device being configured to maintain a routing table for tracking at least one other autonomous memory device of the distributed array, and the routing table enabling the individual autonomous memory device to route a message to the at least one other autonomous memory device. ### Claim 2 (depends on 1) The system of claim 1, wherein the individual autonomous memory device comprises its own operating system. ### Claim 3 (depends on 1) The system of claim 1, wherein the host device is configured to assign a unique static address to each autonomous memory devices of the distributed array. ### Claim 4 (depends on 1) The system of claim 1, wherein the host device is configured to dynamically determine an address of the individual autonomous memory device during an operation of the individual autonomous memory device. ### Claim 5 (depends on 1) The system of claim 1, wherein the individual autonomous memory device is further configured to build the routing table using a scan technique to keep track of remaining autonomous memory devices of the distributed array. ### Claim 6 (depends on 1) The system of claim 1, wherein the individual autonomous memory device is further configured to store a latency cost of communication with the at least one other autonomous memory device based on a location of the individual autonomous memory device. ### Claim 7 (depends on 1) The system of claim 1, wherein the individual autonomous memory device is further configured to execute a search and destroy algorithm simultaneously with one or more other autonomous memory devices of the distributed array to isolate and disable an occurrence of a target virus. ### Claim 8 A system comprising: a host interface to communicate with a host device; and a distributed array of autonomous memory devices implemented by a plurality of die, the distributed array being configured to communicate with the host device by the host interface, a single die of the plurality of die comprising an individual autonomous memory device of the distributed array, the individual autonomous memory device comprising: a microcontroller that is configured to perform computations on a database; a first interface to communicate with the host device by the host interface; and at least one second interface to communicate with at least one other autonomous memory device of the distributed array, the individual autonomous memory device being configured to maintain a routing table for tracking the at least one other autonomous memory device and for storing a latency cost of communication with the at least one other autonomous memory device based on a location of the individual autonomous memory device, and the routing table enabling the individual autonomous memory device to route a message to the at least one other autonomous memory device. ### Claim 9 (depends on 8) The system of claim 8, wherein the individual autonomous memory device further comprises a memory to store information about how the database is organized. ### Claim 10 (depends on 8) The system of claim 8, wherein the individual autonomous memory device is further configured to execute a search and destroy algorithm simultaneously with one or more other autonomous memory devices of the distributed array to isolate and disable an occurrence of a target virus. ### Claim 11 (depends on 8) The system of claim 8, wherein the at least one second interface is configured to transfer messages that comprise a command and a list of parameters to the at least one other autonomous memory device. ### Claim 12 (depends on 11) The system of claim 11, wherein the messages further comprise a transfer of data, address information that refers to data in the distributed array, and object identifiers that reference an object located in the distributed array. ### Claim 13 A system comprising: a host interface to communicate with a host device; and a distributed array of autonomous memory devices implemented by a plurality of die, the distributed array being configured to communicate with the host device by the host interface, a single die of the plurality of die comprising an individual autonomous memory device of the distributed array, the individual autonomous memory device comprising a microcontroller, a memory, and at least one inter-die communication port, and the individual autonomous memory device being configured to: perform computations on a database; maintain a routing table for tracking at least one other autonomous memory device of the distributed array and for storing store a latency cost of communication with the at least one other autonomous memory device based on a location of the individual autonomous memory device, the routing table enabling the individual autonomous memory device to route a message to the at least one other autonomous memory device; and receive the database through the host interface and store the database in the memory, the microcontroller being configured to disperse portions of the database to a neighboring autonomous memory device of the distributed array through the at least one inter-die communication port. ### Claim 14 (depends on 13) The system of claim 13, wherein the memory is configured to receive software from the host device to allow the individual autonomous memory device to control the at least one other autonomous memory device. ### Claim 15 (depends on 13) The system of claim 13, wherein the individual autonomous memory device is further configured to parse and execute operations autonomously in one or more selected autonomous memory devices of the distributed array. ### Claim 16 (depends on 15) The system of claim 15, wherein the one or more selected autonomous memory devices are configured to accumulate and report results from execution of the operations to the host device when the operations are complete. ### Claim 17 (depends on 13) The system of claim 13, wherein one or more selected autonomous memory devices of the distributed array are configured to execute stored routines, provided by libraries and stored in respective memories of the one or more selected autonomous memory devices, to build applications. ### Claim 18 (depends on 13) The system of claim 13, wherein the individual autonomous memory device further comprises acceleration hardware. ### Claim 19 (depends on 13) The system of claim 13, wherein the at least one inter-die communication port comprises a plurality of inter-die communication ports that enable the individual autonomous memory device to communicate simultaneously with a plurality of nearest-neighbor autonomous memory devices of the distributed array. ### Claim 20 (depends on 13) The system of claim 13, wherein the individual autonomous memory device further comprises at least one autonomous memory management mechanism, the at least one autonomous memory management mechanism comprising at least one of a wear leveling mechanism, an error detection and correction mechanism, or a compression and decompression mechanism.