# US 2020/0401549 A1 · Multi-i/o serial peripheral interface for precision converters

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- Number: US 2020/0401549 A1
- Document ID: US20200401549A1
- Status: Published application
- Kind: A1
- Application number: 16/879,205
- Filed: 2020-05-20
- Published: 2020-12-24
- Earliest claimed: 2019-06-20
- Assignees: Analog Devices International Unlimited Company
- Applicants: Analog Devices International Unlimited Company
- Inventors: Miguel Usach Merino; Wes Vernon Lofamia; Fergus John Downey; David A. Browne; Thomas Murphy
- Web page: https://patentgrep.com/patent/US20200401549A1

## CPC

- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 13/4291: {using a clocked protocol}
- G06F 9/30101: {Special purpose registers}
- G06F 9/30189: {according to execution mode, e.g. mode flag}
- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 12/0882: Page mode
- G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)}
- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM}
- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 7/1045: {Read-write mode select circuits}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A Multi-I/O SPI for precision converters supports a Dual/Quad/Octal SPI to support the speed requirements for digital transmission and also includes a special mode that can be enabled by hardware and/or software to remove the bit scrambling requirement dictated by the JEDEC standard. The special mode removes the scramble requirement and associates each of the bidirectional data lines to a specific channel. The special mode provides backward compatibility that permits the precision converter to be used with controllers that do not natively support the JEDEC standard. Also, the Multi-I/O SPI includes registers divided into a primary region that is accessed only in default mode at power-up for write and/or read operations, and a secondary region that is accessed by any mode enabled in the control register. By restricting access to the “control” register area to a pre-defined mode in the converter at power-up, the access mode can be controlled.

## Claims

### Claim 1

A Multi-I/O serial peripheral interface (SPI)), comprising:
a controller having registers divided into a primary region and a secondary region, the primary region including data for configuring the controller and data about errors, and the secondary region including data for providing at least one of a digital to analog converter (DAC) operation or an analog to digital converter (ADC) operation;
a slave device that transfers data to/from the controller via respective data lines; and
a mode selector adapted to select a default mode at power-up wherein the primary region is accessed in the default mode only for write and/or read operations and the secondary region is accessed by any mode enabled by the primary region.

### Claim 2 (depends on 1)

The interface of claim 1, wherein the primary region contains at least one register that stores at least one of data supporting interface configuration, data supporting errors, data supporting power modes, data for configuring the controller, data describing controller behaviour, or data for providing error checks and status.

### Claim 3 (depends on 2)

The interface of claim 2, wherein the primary region contains data identifying a voltage span range of the DAC operation or the ADC operation.

### Claim 4 (depends on 1)

The interface of claim 1, wherein the secondary region contains at least one register that controls the input data and at least one of the DAC operation or the ADC operation.

### Claim 5 (depends on 4)

The interface of claim 4, wherein the secondary region contains a page mask.

### Claim 6 (depends on 1)

The interface of claim 1, wherein the slave device comprises at least one internal fuse or at least one switch adapted to provide a power-up mode select function that defines an interface mode at power-up of the slave device.

### Claim 7 (depends on 1)

The interface of claim 1, wherein the mode selector comprises a mode selection pin on the slave device that is adapted to provide a power-up mode select function that defines an interface mode at power-up of the slave device.

### Claim 8 (depends on 7)

The interface of claim 7, wherein the mode selection pin on the slave device is connected to a first voltage to set the controller and slave device in a first default mode at power up in which the SPI is configured for accessing only the primary region.

### Claim 9 (depends on 8)

The interface of claim 8, further comprising an error pin connecting the slave device to the controller, wherein the primary region comprises error registers, and wherein in the first default mode, the slave device triggers the error pin and pulls the error registers after the slave device has been initialized.

### Claim 10 (depends on 7)

The interface of claim 7, wherein the mode selection pin on the slave device is connected to a second voltage to set the controller and slave device in a second default mode at power up in which the controller reconfigures the SPI in a dual, quad, or octal SPI mode to access the primary region and the secondary region using two, four, or eight data lines, respectively.

### Claim 11 (depends on 1)

The interface of claim 1, wherein the controller has at least two SPI blocks having internally synchronized clock signals, each SPI block transferring data simultaneously, wherein the slave device transfers data to/from each SPI block of the controller via the respective data lines.

### Claim 12 (depends on 11)

The interface of claim 11, wherein the mode selector is further adapted to select a first mode for transferring data between the slave device and each SPI block of the controller in a bits scrambling format dictated by a memory transfer standard or a second mode for transferring data between the slave device and each SPI block of the controller without the bits scrambling format dictated by the memory transfer standard.

### Claim 13 (depends on 12)

The interface of claim 12, wherein the memory transfer standard comprises a JEDEC flash memory communication standard.

### Claim 14

A method for powering up a Multi-I/O serial peripheral interface (SPI)), comprising:
providing a controller having registers divided into a primary region and a secondary region, the primary region including data for configuring the controller and data about errors, and the secondary region including data for providing at least one of a digital to analog converter (DAC) operation or an analog to digital converter (ADC) operation; and
selecting a default mode at power-up in which the primary region is accessed in the default mode only for write and/or read operations and the secondary region is accessed by any mode enabled by the primary region.

### Claim 15 (depends on 14)

The method of claim 14, further comprising storing in at least one register of the primary region at least one of data supporting interface configuration, data supporting errors, data supporting power modes, data for configuring the controller, data describing controller behaviour, or data for providing error checks and status.

### Claim 16 (depends on 15)

The method of claim 15, further comprising storing in the primary region data identifying a voltage span range of the DAC operation or the ADC operation.

### Claim 17 (depends on 14)

The method of claim 14, further comprising setting a mode selection pin on a slave device that that transfers data to/from the controller via respective data lines, the mode selection pin providing a power-up mode select function that defines an interface mode at power-up of the slave device.

### Claim 18 (depends on 17)

The method of claim 17, further comprising connecting the mode selection pin on the slave device to a first voltage to set the controller and slave device in a first default mode at power up in which the SPI is configured for accessing only the primary region.

### Claim 19 (depends on 18)

The method of claim 18, further comprising the slave device triggering, in the first default mode, an error pin connecting the slave device to the controller, the error pin pulling error registers of the primary region after the slave device has been initialized.

### Claim 20 (depends on 17)

The method of claim 17, further comprising connecting the mode selection pin on the slave device to a second voltage to set the controller and slave device in a second default mode at power up in which the controller reconfigures the SPI in a dual, quad, or octal SPI mode to access the primary region and the secondary region using two, four, or eight data lines, respectively.