# US 2020/0401548 A1 · Embedded controller, electronic device, and method for filtering spi bus command in relation to write protection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0401548 A1 - Document ID: US20200401548A1 - Status: Published application - Kind: A1 - Application number: 16/673,609 - Filed: 2019-11-04 - Published: 2020-12-24 - Earliest claimed: 2019-06-21 - Assignees: Hong Fu Jin Precision Industry (Wuhan) Co., Ltd.; Hon Hai Precision Industry Co., Ltd. - Applicants: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD.; Hon Hai Precision Industry Co., Ltd. - Inventors: HUNG-CHI HUANG - Web page: https://patentgrep.com/patent/US20200401548A1 ## CPC - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 9/4401: Bootstrapping (security arrangements therefor G06F21/57) - G06F 13/1642: {with request queuing} - G06F 13/1668: {Details of memory controller} - G06F 21/57: Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities - G06F 21/78: to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) - G06F 13/4291: {using a clocked protocol} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An embedded controller connected with a main control module through a first interface module is connected with an SPI storage through a second interface module. The main control module outputs SPI bus commands to an SPI storage through the embedded controller. The embedded controller includes an EC FW block and an SPI bus command filter module. The EC FW block stores at least one limited SPI bus command. The SPI bus command filter module can switch between an enable mode and a disable mode. In the enable mode, the SPI bus command filter module filters out the SPI bus command from the main control module based on the at least one limited SPI bus command, and blocks the SPI bus command, thus performing a write protection of the SPI storage. ## Claims ### Claim 1 An embedded controller connected with a main control module through a first interface module, and connected with an SPI storage through a second interface module; the main control module outputting SPI bus commands to the SPI storage through the embedded controller; the embedded controller comprising: a BIOS block configured to store program codes; a EC FW block configured to store at least one limited SPI bus command; and an SPI bus command filter module configured to filter the SPI bus command; wherein the SPI bus command filter module is capable of switching between an enable mode and a disable mode; in the enable mode, the SPI bus command filter module filters the SPI bus command from the main control module based on the at least one limited SPI bus command, and blocks the SPI bus command for performing a written protection of the SPI storage when the SPI bus commands with the at least one limited SPI bus command. ### Claim 2 (depends on 1) The embedded controller of claim 1, wherein the embedded controller further connected with a disable jumper; the disable jumper switches between an enable state and a disable state; the disable jumper controls the embedded controller to switch between the enable mode and the disable mode. ### Claim 3 (depends on 2) The embedded controller of claim 2, wherein the SPI bus command filter module comprises a detection unit and a filter unit; the detection unit detects whether the disable jumper is in the enable state; when the disable jumper is in the enable state, the detection unit outputs a disable control signal, and the filter unit directly outputs the SPI bus commands to the SPI storage based on the disable control signal; when the disable jumper is in the disable state, the detection unit outputs an enable control signal, and the filter unit compares the SPI bus command with the at least one limited SPI bus command based on the enable control signal. ### Claim 4 (depends on 1) The embedded controller of claim 1, wherein the SPI bus command filter module further comprises a rewrite unit; the rewrite unit rewires the at least one limited SPI bus command in the EC FW block in response to a rewrite instruction. ### Claim 5 An electronic device comprising: a main control module comprising a CPU and a PCH; the PCH configured to generate SPI bus commands; an SPI storage comprising a BIOS block and an EC FW block; the BIOS block; the BIOS block configured to store program codes, and the EC FW block configured to store at least one limited SPI bus command; and an embedded controller configured to connect with PCH through a first interface module, and connect with the SPI storage through a second interface module; wherein the embedded controller further comprises an SPI bus command filter module; the SPI bus command filter module is capable of switching between an enable mode and a disable mode; in the enable mode, the SPI bus command filter module filters the SPI bus command from the main control module based on the at least one limited SPI bus command, and blocks the SPI bus command for performing a written protection of the SPI storage when the SPI bus commands with the at least one limited SPI bus command. ### Claim 6 (depends on 5) The electronic device of claim 5, wherein the embedded controller further connected with a disable jumper; the disable jumper switches between an enable state and a disable state; the disable jumper controls the embedded controller to switch between the enable mode and the disable mode. ### Claim 7 (depends on 6) The electronic device of claim 6, wherein the SPI bus command filter module comprises a detection unit and a filter unit; the detection unit detects whether the disable jumper is in the enable mode; when the disable jumper is in the enable state, the detection unit outputs a disable control signal, and the filter unit directly outputs the SPI bus commands to the SPI storage based on the disable control signal; when the disable jumper is in the disable state, the detection unit outputs an enable control signal, and the filter unit compares the SPI bus command with the at least one limited SPI bus command based on the enable control signal. ### Claim 8 (depends on 5) The electronic device of claim 5, wherein the SPI bus command filter module further comprises a rewrite unit; the rewrite unit rewires the at least one limited SPI bus command in the EC FW block in response to a rewrite instruction. ### Claim 9 A SPI bus command filter method provided to an electronic device for performing a write protection; the electronic device comprising a main control module, an SPI storage, and an embedded controller; the embedded controller comprising an SPI bus command filter module; the SPI bus command filter module comprising a detection unit and a filter unit; the SPI storage comprising a BIOS block and a EC FW block; the BIOS block storing operation codes; the EC FW block storing at least one limited SPI bus command; the SPI bus command filter method comprising: initializing the electronic device and generating SPI bus commands by a PCH of the main control module; detecting whether a disable jumper is in an enable state; outputting an enable control signal when the disable jumper is in a disable state; determining whether the SPI bus command comprises the at least one limited SPI bus command based on the enable control signal; blocking the SPI bus command when the SPI bus command comprises the at least one limited SPI bus command. ### Claim 10 (depends on 9) The SPI bus command filter method of claim 9, further comprising: outputting a disable control signal for disabling a filter function of the filter unit when the disable jumper is in the enable state; outputting the SPI bus command to the SPI storage through the second interface module. ### Claim 11 (depends on 9) The SPI bus command filter method of claim 9, further comprising: outputting the SPI bus command to the SPI storage through the second interface module when the SPI bus command without the at least one limited SPI bus command. ### Claim 12 (depends on 9) The SPI bus command filter method of claim 9, further comprising: rewriting the at least one limited SPI bus command in response to a rewrite instruction.