# US 2020/0401541 A1 · Unified cache for diverse memory traffic

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- Number: US 2020/0401541 A1
- Document ID: US20200401541A1
- Status: Published application
- Kind: A1
- Application number: 16/921,795
- Filed: 2020-07-06
- Published: 2020-12-24
- Earliest claimed: 2017-05-04
- Assignees: NVIDIA Corporation
- Applicants: NVIDIA Corporation
- Inventors: Xiaogang QIU; Ronny KRASHINSKY; Steven HEINRICH; Shirish GADRE; John EDMONDSON; Jack CHOQUETTE; Mark GEBHART; Ramesh JANDHYALA; Poornachandra RAO; Omkar PARANJAPE; Michael SIU
- Web page: https://patentgrep.com/patent/US20200401541A1

## CPC

- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/084: with a shared cache
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 12/122: of the least frequently used [LFU] type, e.g. with individual count value
- G06F 2212/60: Details of cache memory
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- G06F 2213/28: DMA
- G11C 7/1015: {Read-write modes for single port memories, i.e. having either a random port or a serial port}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.

## Claims

### Claim 1

(canceled)

### Claim 2

A memory subsystem, comprising:
a first memory; and
address logic that routes first-type memory transactions along a first data pathway directly to the first memory, and routes second-type memory transactions either along the first data pathway directly to the first memory or along a second data pathway to a second memory depending on whether data associated with the second-type memory transactions is resident in the first memory.

### Claim 3 (depends on 2)

The memory subsystem of claim 2, further comprising a third memory that stores tags, wherein the address logic determines whether the data associated with the second-type memory transactions is resident in the first memory based on whether tags associated with the second-type memory transactions are stored in the third memory.

### Claim 4 (depends on 2)

The memory subsystem of claim 2, wherein, when the data associated with the second-type memory transactions is not resident in the first memory, the address logic stores the second-type memory transactions in a tag-to-data first-in first-out buffer until the data associated with the second-type memory transactions is returned to the first memory.

### Claim 5 (depends on 2)

The memory subsystem of claim 2, wherein the first-type memory transactions target shared memory, and the second-type memory transactions target at least one of local memory or global memory.

### Claim 6 (depends on 2)

The memory subsystem of claim 2, wherein the address logic routes texture-oriented memory transactions from a texture processing pipeline along the second pathway, and data is read from the first memory via a crossbar that is shared between at least one processing core and the texture processing pipeline.

### Claim 7 (depends on 2)

The memory subsystem of claim 2, wherein the first memory comprises a plurality of sub-banks, and the address logic coalesces two or more memory transactions that target a same sub-bank.

### Claim 8 (depends on 2)

The memory subsystem of claim 2, further comprising a processor that appends a token to a second-type memory transaction when data associated with the second-type memory transaction is not resident in the first memory.

### Claim 9 (depends on 2)

The memory subsystem of claim 2, further comprising a data scrubber that maintains data slot availability in the first memory above a predefined threshold.

### Claim 10 (depends on 9)

The memory subsystem of claim 9, wherein the data scrubber stores tags in a third memory to cause corresponding data slots in the first memory to be allocated, and evicts tags stored in the third memory to cause data stored in corresponding data slots in the first memory to be evicted.

### Claim 11 (depends on 9)

The memory subsystem of claim 9, wherein the data scrubber increments an age counter associated with a class to cause data associated with the class that is stored in the first memory to be evicted when a request is received to access the data associated with the class.

### Claim 12

A system, comprising:
a streaming multiprocessor that generates first-type memory transactions and second-type memory transactions; and
a unified cache comprising a first memory, wherein the unified cache is coupled to the streaming multiprocessor and services the first-type memory transactions and the second-type memory transactions by performing the steps of:
routing the first-type memory transactions along a first data pathway directly to the first memory, and
routing the second-type memory transactions either along the first data pathway directly to the first memory or along a second data pathway to a second memory depending on whether data associated with the second-type memory transactions is resident in the first memory.

### Claim 13 (depends on 12)

The system of claim 12, wherein the unified cache further comprises a third memory that stores tags, and the unified cache determines whether the data associated with the second-type memory transactions is resident in the first memory based on whether tags associated with the second-type memory transactions are stored in the third memory.

### Claim 14 (depends on 12)

The system of claim 12, wherein, when the data associated with the second-type memory transactions is not resident in the first memory, the unified cache stores the second-type memory transactions in a tag-to-data first-in first-out buffer until the data associated with the second-type memory transactions is returned to the first memory.

### Claim 15 (depends on 12)

The system of claim 12, wherein the first-type memory transactions target shared memory, and the second-type memory transactions target at least one of local memory or global memory.

### Claim 16 (depends on 12)

The system of claim 12, wherein the unified cache routes texture-oriented memory transactions from a texture processing pipeline along the second pathway, and data is read from the first memory via a crossbar that is shared between at least one processing core and the texture processing pipeline.

### Claim 17 (depends on 12)

The system of claim 12, wherein the first memory comprises a plurality of sub-banks, and the unified cache coalesces two or more memory transactions that target a same sub-bank.

### Claim 18 (depends on 12)

The system of claim 12, wherein the unified cache further comprises a data scrubber that maintains data slot availability in the first memory above a predefined threshold.

### Claim 19 (depends on 18)

The system of claim 18, wherein the data scrubber stores tags in a third memory to cause corresponding data slots in the first memory to be allocated, and evicts tags stored in the third memory to cause data stored in corresponding data slots in the first memory to be evicted.

### Claim 20 (depends on 18)

The system of claim 18, wherein the data scrubber increments an age counter associated with a class to cause data associated with the class that is stored in the first memory to be evicted when a request is received to access the data associated with the class.

### Claim 21 (depends on 12)

The system of claim 12, wherein the system comprises a computing device.

### Claim 22 (depends on 21)

The system of claim 21, wherein the computing device comprises one of a desktop computer, a laptop computer, a handheld personal computer, a handheld device, a server, a workstation, a game console, or an embedded system.

### Claim 23

A computer-implemented method for servicing memory transactions, the method comprising:
receiving first-type memory transactions and second-type memory transactions;
routing the first-type memory transactions along a first data pathway directly to a first memory; and
routing the second-type memory transactions either along the first data pathway directly to the first memory or along a second data pathway to a second memory depending on whether data associated with the second-type memory transactions is resident in the first memory.