# US 2020/0401540 A1 · DMA-Scatter and Gather Operations for Non-Contiguous Memory

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- Number: US 2020/0401540 A1
- Document ID: US20200401540A1
- Status: Published application
- Kind: A1
- Application number: 16/906,262
- Filed: 2020-06-19
- Published: 2020-12-24
- Earliest claimed: 2019-06-21
- Assignees: Microchip Technology Incorporated
- Applicants: Microchip Technology Incorporated
- Inventors: Laurentiu Birsan; Manish Patel; Joseph Triece
- Web page: https://patentgrep.com/patent/US20200401540A1

## CPC

- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A direct memory access (DMA) controller, includes circuitry configured to load a DMA transfer descriptor configured to define which memory elements within a contiguous block of n memory elements are to be included in a given DMA transfer. The circuitry is further configured to, based on the DMA transfer descriptor, determine whether each memory element within the contiguous block of n memory elements is to be included in the given DMA transfer, including a determination that two or more non-contiguous sub-blocks of memory elements within the contiguous block of n memory elements are to be transferred. The circuitry is further configured to, based on the determination of whether each memory element within the contiguous block of n memory elements is to be included in the given DMA transfer, perform the DMA transfer of memory elements determined to be included within the given DMA transfer.

## Claims

### Claim 1

A direct memory access (DMA) controller, including circuitry configured to:
load a first DMA transfer descriptor, the first DMA transfer descriptor configured to define which memory elements within a first contiguous block of n memory elements are to be included in a given DMA transfer;
based on the first DMA transfer descriptor, determine whether each memory element within the first contiguous block of n memory elements is to be included in the given DMA transfer, including a determination that a plurality of non-contiguous sub-blocks of memory elements within the first contiguous block of n memory elements are to be transferred; and
based on the determination of whether each memory element within the first contiguous block of n memory elements is to be included in the given DMA transfer, perform the DMA transfer of memory elements determined to be included within the given DMA transfer.

### Claim 2 (depends on 1)

The DMA controller of claim 1, wherein the circuitry is further configured to:
determine that additional memory elements are to be included in the given DMA transfer;
load a second DMA transfer descriptor, the second DMA transfer descriptor configured to define which memory elements within a second contiguous block of n memory elements are to be included in a given DMA transfer;
based on the second DMA transfer descriptor, determine whether each memory element within the second contiguous block of n memory elements is to be included in the given DMA transfer, including a determination that a plurality of non-contiguous sub-blocks of memory elements within the second contiguous block of n memory elements are to be transferred; and
based on the determination of whether each memory element within the second contiguous block of n memory elements is to be included in the given DMA transfer, perform the DMA transfer of memory elements determined to be included within the given DMA transfer.

### Claim 3 (depends on 2)

The DMA controller of claim 2, wherein the circuitry is further configured to determine that additional memory elements are to be included in the given DMA transfer from information included in the first DMA transfer descriptor.

### Claim 4 (depends on 2)

The DMA controller of claim 2, wherein the circuitry is further configured to determine an address of the second DMA transfer descriptor from information included in the first DMA transfer descriptor.

### Claim 5 (depends on 2)

The DMA controller of claim 2, wherein the first and second contiguous blocks of n memory elements to be included in the given DMA transfer are within a same peripheral.

### Claim 6 (depends on 2)

The DMA controller of claim 2, wherein the first and second contiguous blocks of n memory elements to be included in the given DMA transfer are within a different peripheral.

### Claim 7 (depends on 2)

The DMA controller of claim 2, wherein the first DMA transfer descriptor is configured to define all of the plurality of non-contiguous sub-blocks within the first contiguous block of n memory elements are to be transferred.

### Claim 8 (depends on 1)

The DMA controller of claim 1, wherein the first DMA transfer descriptor is further configured to define the plurality of non-contiguous sub-blocks of memory elements within the first contiguous block of n memory elements.

### Claim 9 (depends on 8)

The DMA controller of claim 8, wherein the first DMA transfer descriptor is further configured to define a first memory element within the first contiguous block of n memory elements to be included in the given DMA transfer by a base address of the first contiguous block of n memory elements.

### Claim 10 (depends on 8)

The DMA controller of claim 8, wherein the first DMA transfer descriptor is further configured to define one or more second memory elements within the first contiguous block of n memory elements to be included in the given DMA transfer by a plurality of indicators.

### Claim 11 (depends on 10)

The DMA controller of claim 10, wherein the plurality of indicators includes a series of bits, each bit configured to indicate whether an associated memory element is to be included in the given DMA transfer.

### Claim 12 (depends on 11)

The DMA controller of claim 11, wherein the series of bits includes n bits.

### Claim 13 (depends on 12)

The DMA controller of claim 12, wherein one of then bits is configured to indicate that additional memory elements are to be included in the given DMA transfer.

### Claim 14 (depends on 1)

The DMA controller of claim 1, wherein the first contiguous block of n memory elements to be included in the given DMA transfer is within a register bank and the first contiguous block of n memory elements to be included in the given DMA transfer has a different base address than the register bank.

### Claim 15

A method for direct memory access (DMA) control, including:
loading a first DMA transfer descriptor, the first DMA transfer descriptor defining which memory elements within a first contiguous block of n memory elements are to be included in a given DMA transfer;
based on the first DMA transfer descriptor, determining whether each memory element within the first contiguous block of n memory elements is to be included in the given DMA transfer, including a determination that a plurality of non-contiguous sub-blocks of memory elements within the first contiguous block of n memory elements are to be transferred; and
based on the determination of whether each memory element within the first contiguous block of n memory elements is to be included in the given DMA transfer, performing the DMA transfer of memory elements determined to be included within the given DMA transfer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
determining that additional memory elements are to be included in the given DMA transfer;
loading a second DMA transfer descriptor, the second DMA transfer descriptor configured to define which memory elements within a second contiguous block of n memory elements are to be included in a given DMA transfer;
based on the second DMA transfer descriptor, determining whether each memory element within the second contiguous block of n memory elements is to be included in the given DMA transfer, including a determination that a plurality of non-contiguous sub-blocks of memory elements within the second contiguous block of n memory elements are to be transferred; and
based on the determination of whether each memory element within the second contiguous block of n memory elements is to be included in the given DMA transfer, performing the DMA transfer of memory elements determined to be included within the given DMA transfer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising determining that additional memory elements are to be included in the given DMA transfer from information included in the first DMA transfer descriptor.

### Claim 18 (depends on 16)

The method of claim 16, further comprising determining an address of the second DMA transfer descriptor from information included in the first DMA transfer descriptor.

### Claim 19 (depends on 16)

The method of claim 16, further comprising, defining, in the first DMA transfer descriptor, all of the plurality of non-contiguous sub-blocks within the first contiguous block of n memory elements are to be transferred.

### Claim 20 (depends on 15)

The method of claim 15, further comprising, wherein the first DMA transfer descriptor is further configured to define the plurality of non-contiguous sub-blocks of memory elements within the first contiguous block of n memory elements.