# US 2020/0401538 A1 · Integrated circuits for generating input/output latency performance metrics using real-time clock (rtc) read measurement module

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- Number: US 2020/0401538 A1
- Document ID: US20200401538A1
- Status: Published application
- Kind: A1
- Application number: 16/445,500
- Filed: 2019-06-19
- Published: 2020-12-24
- Earliest claimed: 2019-06-19
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Garrett Matthias Drown; Patrick Lu
- Web page: https://patentgrep.com/patent/US20200401538A1

## CPC

- G06F 3/0671: {In-line storage system}
- G06F 13/20: for access to input/output bus
- G06F 3/0605: {by facilitating the interaction with a user or administrator}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 9/30098: {Register arrangements}
- G06F 13/126: {and has means for transferring I/O instructions and statuses between control unit and main processor}
- G06F 3/00: Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F 2213/0026: PCI express
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An integrated circuit includes technology for generating input/output (I/O) latency metrics. The integrated circuit includes a real-time clock (RTC), a read measurement register, and a read latency measurement module. The read latency measurement module includes control logic to perform operations comprising (a) in response to receipt of read responses that complete read requests associated with an I/O device, automatically calculating read latencies for the completed read requests, based at least in part on time measurements from the RTC for initiation and completion of the read requests; (b) automatically calculating an average read latency for the completed read requests, based at least in part on the calculated read latencies for the completed read requests; and (c) automatically updating the read measurement register to record the average read latency for the completed read requests. Other embodiments are described and claimed.

## Claims

### Claim 1

An integrated circuit with technology for generating input/output latency metrics, the integrated circuit comprising:
a real-time clock (RTC);
a read measurement register; and
a read latency measurement module, wherein the read latency measurement module comprises control logic to perform operations comprising:
in response to receipt of read responses that complete read requests associated with an input/output (I/O) device, automatically calculating read latency for the completed read requests, based at least in part on time measurements from the RTC for initiation and completion of the completed read requests;
automatically calculating an average read latency for the completed read requests, based at least in part on the calculated read latencies for the completed read requests; and
automatically updating the read measurement register to record the average read latency for the completed read requests.

### Claim 2 (depends on 1)

An integrated circuit according to claim 1, wherein the read latency monitor further comprises control logic to perform operations comprising:
automatically determining a minimum read latency for the completed read requests;
automatically determining a maximum read latency for the completed read requests; and
automatically updating the read measurement register to record the minimum read latency and the maximum read latency.

### Claim 3 (depends on 1)

An integrated circuit according to claim 1, further comprising:
an I/O manager to manage the read requests, wherein the I/O manager comprises the RTC, the read measurement register, and the read latency measurement module.

### Claim 4 (depends on 3)

An integrated circuit according to claim 3, wherein:
the I/O manager is configured to send a device read request to the I/O device in response to receiving a host read request from a processing core; and
the completed read requests comprise device read requests.

### Claim 5 (depends on 4)

An integrated circuit according to claim 4, wherein the I/O manager complies with revision 3.0 of a Peripheral Component Interconnect Express (PCIe) base specification.

### Claim 6 (depends on 5)

An integrated circuit according to claim 5, wherein the I/O manager comprises a PCIe root complex.

### Claim 7 (depends on 3)

A central processing unit (CPU) comprising:
the integrated circuit according to claim 3; and
a processing core in the integrated circuit to send host read requests to the I/O manager.

### Claim 8 (depends on 7)

A data processing system comprising:
the CPU according to claim 7; and
the I/O device.

### Claim 9 (depends on 8)

A data processing system according to claim 8, wherein:
the I/O manager comprises a root port connected to multiple I/O devices; and
the operation of automatically calculating average read latency for the completed read requests comprises of automatically calculating average read latency for completed read requests involving any of the I/O devices connected to the root port.

### Claim 10

A data processing system with technology for generating input/output latency metrics, the data processing system comprising:
an input/output (I/O) manager;
an I/O device responsive to the I/O manager;
a central processing unit (CPU) to communicate with the I/O device via the I/O manager;
a real-time clock (RTC) in the I/O manager;
a read measurement register in the I/O manager; and
a read latency measurement module in the I/O manager, wherein the read latency measurement module comprises control logic to perform operations comprising:
in response to receipt of read responses that complete read requests associated with the I/O device, automatically calculating read latency for the completed read requests, based at least in part on time measurements from the RTC for initiation and completion of the completed read requests;
automatically calculating an average read latency for the completed read requests, based at least in part on the calculated read latencies for the completed read requests; and
automatically updating the read measurement register to record the average read latency for the completed read requests.

### Claim 11 (depends on 10)

A data processing system according to claim 10, wherein the read latency monitor further comprises control logic to perform operations comprising:
automatically determining a minimum read latency for the completed read requests;
automatically determining a maximum read latency for the completed read requests; and
automatically updating the read measurement register to record the minimum read latency and the maximum read latency.

### Claim 12 (depends on 10)

A data processing system according to claim 10, wherein:
the I/O manager is configured to send a device read request to the I/O device in response to receiving a host read request from a processing core; and
the completed read requests comprise device read requests.

### Claim 13 (depends on 12)

A data processing system according to claim 12, wherein the I/O manager complies with revision 3.0 of a Peripheral Component Interconnect Express (PCIe) base specification.

### Claim 14 (depends on 13)

A data processing system according to claim 13, wherein the I/O manager comprises a PCIe root complex.

### Claim 15 (depends on 10)

A data processing system according to claim 10, wherein:
the I/O manager comprises a root port connected to multiple I/O devices; and
the operation of automatically calculating average read latency for the completed read requests comprises of automatically calculating average read latency for completed read requests involving any of the I/O devices connected to the root port.

### Claim 16

A method for generating input/output latency metrics, the method comprising:
at a read latency measurement module in an input/output (I/O) manager of a data processing system, in response to receipt of read responses that complete read requests associated with an I/O device, automatically calculating read latencies for the completed read requests, based at least in part on time measurements from a real-time clock (RTC) for initiation and completion of the completed read requests;
at the read latency measurement module, automatically calculating an average read latency for the completed read requests, based at least in part on the calculated read latencies for the completed read requests; and
automatically updating a read measurement register in the I/O manager to record the average read latency for the completed read requests.

### Claim 17 (depends on 16)

A method according to claim 16, further comprising:
at the read latency measurement module, automatically determining a minimum read latency for the completed read requests and automatically determining a maximum read latency for the completed read requests; and
automatically updating the read measurement register to record the minimum read latency and the maximum read latency.

### Claim 18 (depends on 16)

A method according to claim 16, further comprising:
at the I/O manager, receiving a host read request from a processing core of the data processing system; and
automatically sending a device read request from the I/O manager to the I/O device, in response to receiving the host read request from the processing core; and
wherein the completed read requests comprise device read requests.

### Claim 19 (depends on 18)

A method according to claim 18, further comprising:
at the I/O manager, managing read requests as a Peripheral Component Interconnect Express (PCIe) root complex, in accordance with revision 3.0 of a PCIe base specification.

### Claim 20 (depends on 16)

A method according to claim 16, further comprising:
receiving the read responses via a root port of the I/O manager that is connected to multiple I/O devices; and
wherein the operation of automatically calculating average read latency for the completed read requests comprises of automatically calculating average read latency for completed read requests involving any of the I/O devices connected to the root port.

### Claim 21

An integrated circuit with technology for generating input/output latency metrics, the integrated circuit comprising:
an input/output (I/O) manager to manage read requests, wherein the I/O manager complies with revision 3.0 of a Peripheral Component Interconnect Express (PCIe) base specification;
a real-time clock (RTC) in the I/O manager;
a read measurement register in the I/O manager; and
a read latency measurement module in the I/O manager, wherein the read latency measurement module comprises control logic to perform operations comprising:
in response to receipt of read responses that complete read requests associated with an I/O device, automatically calculating read latency for the completed read requests, based at least in part on time measurements from the RTC for initiation and completion of the completed read requests;
automatically calculating an average read latency for the completed read requests, based at least in part on the calculated read latencies for the completed read requests; and
automatically updating the read measurement register to record the average read latency for the completed read requests.

### Claim 22 (depends on 21)

An integrated circuit according to claim 21, wherein the read latency monitor further comprises control logic to perform operations comprising:
automatically determining a minimum read latency for the completed read requests;
automatically determining a maximum read latency for the completed read requests; and
automatically updating the read measurement register to record the minimum read latency and the maximum read latency.

### Claim 23 (depends on 21)

An integrated circuit according to claim 21, wherein the I/O manager comprises a PCIe root complex.