# US 2020/0401536 A1 · Wave pipeline including synchronous stage

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- Number: US 2020/0401536 A1
- Document ID: US20200401536A1
- Status: Published application
- Kind: A1
- Application number: 16/448,188
- Filed: 2019-06-21
- Published: 2020-12-24
- Earliest claimed: 2019-06-21
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Kaveh Shakeri; Ali Feiz Zarrin Ghalam
- Web page: https://patentgrep.com/patent/US20200401536A1

## CPC

- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/32: Timing circuits
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage between a data input node and a data output node. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The clock path includes a plurality of clock stages corresponding to the plurality of wave pipeline data stages between an input clock node and a return clock node. Each clock stage has a delay configured to be equal to a delay of the corresponding wave pipeline data stage. The wave pipeline includes a second data latch to latch the data on the data output node in response to a return clock signal on the return clock node. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

## Claims

### Claim 1

A wave pipeline comprising:
a data path comprising a plurality of wave pipeline data stages and a synchronous data stage between a data input node and a data output node, the synchronous data stage comprising a first data latch to latch the data from the synchronous data stage;
a clock path comprising a plurality of clock stages corresponding to the plurality of wave pipeline data stages between an input clock node and a return clock node, each clock stage of the plurality of clock stages having a delay configured to be equal to a delay of the corresponding wave pipeline data stage of the plurality of wave pipeline data stages; and
a second data latch to latch the data on the data output node in response to a return clock signal on the return clock node,
wherein the first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

### Claim 2 (depends on 1)

The wave pipeline of claim 1, wherein the second data latch comprises a FIFO.

### Claim 3 (depends on 2)

The wave pipeline of claim 2, wherein the FIFO comprises a plurality of stages equal to the number of clock stages of the plurality of clock stages.

### Claim 4 (depends on 1)

The wave pipeline of claim 1, wherein the synchronous data stage is between a first wave pipeline data stage and a second wave pipeline data stage of the plurality of wave pipeline data stages.

### Claim 5 (depends on 1)

The wave pipeline of claim 1, wherein the plurality of wave pipeline data stages comprises at least two wave pipeline data stages.

### Claim 6 (depends on 1)

The wave pipeline of claim 1, wherein a delay of each wave pipeline data stage of the plurality of wave pipeline data stages is less than one cycle of the clock signal.

### Claim 7 (depends on 1)

The wave pipeline of claim 1, wherein a delay of the synchronous data stage is less than one cycle of the clock signal.

### Claim 8 (depends on 1)

The wave pipeline of claim 1, wherein a delay of the synchronous data stage is greater than one cycle of the clock signal, and
wherein the clock path further comprises a delay stage such that the first data latch latches the data from the synchronous data stage in response to a delayed clock signal from the delay stage.

### Claim 9 (depends on 8)

The wave pipeline of claim 8, wherein a delay of the delay stage is less than a delay of the synchronous data stage.

### Claim 10 (depends on 1)

The wave pipeline of claim 1, wherein the data path comprises a plurality of synchronous data stages between the data input node and the data output node, each synchronous data stage of the plurality of synchronous data stages comprising a first data latch to latch the data from the corresponding synchronous data stage of the plurality of synchronous data stages, and
wherein each first data latch of the plurality of synchronous data stages latches the data from the corresponding synchronous data stage in response to the clock signal on the clock path.

### Claim 11

A memory comprising:
a memory array;
a synchronous data stage to output data from the memory array in response to an address signal, the synchronous data stage comprising a first data latch to latch the output data;
an address path coupled to an input of the synchronous data stage, the address path comprising a plurality of wave pipeline address stages;
a data path coupled to an output of the synchronous data stage, the data path comprising a plurality of wave pipeline data stages;
an input clock path comprising a plurality of input clock stages corresponding to the plurality of wave pipeline address stages, each input clock stage of the plurality of input clock stages comprising a delay configured to be equal to a delay of the corresponding wave pipeline address stage of the plurality of wave pipeline address stages; and
a return clock path coupled to the input clock path at the first data latch, the return clock path comprising a plurality of return clock stages corresponding to the plurality of wave pipeline data stages, a delay of each return clock stage of the plurality of return clock stages equal to a delay of the corresponding wave pipeline data stage of the plurality of wave pipeline data stages,
wherein the first data latch latches the output data in response to a clock signal on the input clock path.

### Claim 12 (depends on 11)

The memory of claim 11, further comprising:
a FIFO to latch the data from the data path in response to a return clock signal from the return clock path.

### Claim 13 (depends on 12)

The memory of claim 12, wherein the FIFO comprises a plurality of stages equal to the number of input clock stages plus the number of return clock stages.

### Claim 14 (depends on 11)

The memory of claim 11, wherein a delay of each wave pipeline address stage of the plurality of wave pipeline address stages is less than one cycle of the clock signal, and
wherein a delay of each wave pipeline data stage of the plurality of wave pipeline data stages is less than one cycle of the clock signal.

### Claim 15 (depends on 11)

The memory of claim 11, wherein a delay of the synchronous data stage is less than one cycle of the clock signal.

### Claim 16 (depends on 11)

The memory of claim 11, wherein the memory array comprises a NAND memory array.

### Claim 17

A method for processing data through a wave pipeline, the method comprising:
asynchronously processing data through a first wave pipeline data stage;
delaying a clock signal to align the clock signal with the data from the first wave pipeline data stage;
processing the data from the first wave pipeline data stage through a synchronous data stage;
latching the data from the synchronous data stage in response to the delayed clock signal, the delayed clock signal providing a return clock signal;
processing the latched data through a second wave pipeline data stage; and
delaying the return clock signal to align the return clock signal with the data from the second wave pipeline data stage.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
latching the data from the second wave pipeline data stage in response to the delayed return clock signal.

### Claim 19 (depends on 18)

The method of claim 18, wherein latching the data from the second wave pipeline data stage comprises latching the data from the second wave pipeline data stage in a FIFO.

### Claim 20 (depends on 17)

The method of claim 17, wherein processing the data from the first wave pipeline data stage through the synchronous data stage comprises processing the data from the first wave pipeline data stage through the synchronous data stage in less than one cycle of the clock signal.

### Claim 21 (depends on 17)

The method of claim 17, further comprising:
delaying the clock signal aligned with the data from the first wave pipeline data stage,
wherein processing the data from the first wave pipeline data stage through the synchronous data stage comprises processing the data from the first wave pipeline data stage through the synchronous data stage in more than one cycle of the clock signal.