# US 2020/0401533 A1 · Memory device with cryptographic kill switch

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- Number: US 2020/0401533 A1
- Document ID: US20200401533A1
- Status: Published application
- Kind: A1
- Application number: 16/444,359
- Filed: 2019-06-18
- Published: 2020-12-24
- Earliest claimed: 2019-06-18
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Gil Golov
- Web page: https://patentgrep.com/patent/US20200401533A1

## CPC

- G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)}
- H04L 9/0897: {involving additional devices, e.g. trusted platform module [TPM], smartcard or USB}
- G06F 12/1433: {for a module or a part of a module}
- G06F 12/1466: {Key-lock mechanism}
- H04L 9/0825: {using asymmetric-key encryption or public key infrastructure [PKI], e.g. key signature or public key certificates}
- H04L 9/14: using a plurality of keys or algorithms
- H04L 9/30: Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
- G06F 2212/1052: Security improvement
- G06F 2212/173: Vehicle or other transportation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

The disclosed embodiments describe devices and methods for preventing unauthorized access to memory devices. The disclosed embodiments utilize a one-time programmable (OTP) memory added to both a memory device and a processing device. The OTP memory stores encryption keys and the encryption and decryption of messages between the two devices are used as a heartbeat to determine that the memory device has not been separated from the processing device and, in some instances, connected to a malicious processing device.

## Claims

### Claim 1

A method comprising:
transmitting, by a memory device, an encrypted command to a processing device;
receiving, by the memory device, a response from the processing device;
decrypting, by the memory device, the response;
detecting, by the memory device, that the decrypting failed; and
disabling, by the memory device, a command/address interface in response to detecting that the decrypting failed.

### Claim 2 (depends on 1)

The method of claim 1, further comprising generating the encrypted command by encrypting a plaintext command using a shared private key.

### Claim 3 (depends on 2)

The method of claim 2, the decrypting the response comprising decrypting the response using the shared private key.

### Claim 4 (depends on 1)

The method of claim 1, further comprising generating the encrypted command by encrypting a plaintext command using a public key.

### Claim 5 (depends on 4)

The method of claim 4, the decrypting the response comprising decrypting the response using a private key corresponding to the public key.

### Claim 6 (depends on 1)

The method of claim 1, the disabling the command/address interface causing the memory device to ignore any instructions transmitted over the command/address interface.

### Claim 7 (depends on 1)

The method of claim 1 further comprising scrubbing one or more memory banks upon detecting a successful decryption after detecting that the decrypting failed.

### Claim 8 (depends on 1)

The method of claim 1, the detecting that the decrypting failed further comprising determining whether the response is valid or invalid.

### Claim 9

A device comprising:
a memory array;
control logic communicatively coupled to the memory array;
a one-time programmable (OTP) memory bank, the OTP storing at least one key; and
authentication logic the authentication logic configured to:
transmit an encrypted command to a processing device,
receive a response from the processing device,
decrypt the response,
detect that the decrypting failed, and
disable a command/address interface of the control logic in response to detecting that the decrypting failed.

### Claim 10 (depends on 9)

The device of claim 9, the memory array comprising a dynamic random-access memory (DRAM) array.

### Claim 11 (depends on 9)

The device of claim 9, the dedicated interface comprising a serial interface.

### Claim 12 (depends on 9)

The device of claim 9, the at least one key comprising a shared symmetric key.

### Claim 13 (depends on 9)

The device of claim 9, the at least one key comprising a private key unique to the device, and a public key of the processing device, the private key used to decrypt the response and the public key used to encrypt the command.

### Claim 14 (depends on 9)

The device of claim 9, the command/address interface communicatively coupled to a signal generated by the authentication logic, the disabling of the command/address interface comprising raising the signal generated by the authentication logic.

### Claim 15

A non-transitory computer readable storage medium for tangibly storing computer program instructions capable of being executed by a processor, the computer program instructions defining the steps of:
transmitting an encrypted command to a processing device;
receiving a response from the processing device;
decrypting the response;
detecting that the decrypting failed; and
disabling a command/address interface in response to detecting that the decrypting failed.

### Claim 16 (depends on 15)

The computer readable storage medium of claim 15, the instructions further defining the step of generating the encrypted command by encrypting a plaintext command using a shared private key, wherein the decrypting the response comprising decrypting the response using the shared private key.

### Claim 17 (depends on 15)

The computer readable storage medium of claim 15, the instructions further defining the step of generating the encrypted command by encrypting a plaintext command using a public key, wherein the decrypting the response comprising decrypting the response using a private key corresponding to the public key.

### Claim 18 (depends on 15)

The computer readable storage medium of claim 15, the disabling the command/address interface causing the memory device to ignore any instructions transmitted over the command/address interface.

### Claim 19 (depends on 15)

The computer readable storage medium of claim 15 the instructions further defining the step of scrubbing one or more memory banks upon detecting a successful decryption after detecting that the decrypting failed.

### Claim 20 (depends on 15)

The computer readable storage medium of claim 15, the detecting that the decrypting failed further comprising determining whether the response is valid or invalid.