# US 2020/0401532 A1 · Lookahead priority collection to support priority elevation

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- Number: US 2020/0401532 A1
- Document ID: US20200401532A1
- Status: Published application
- Kind: A1
- Application number: 16/916,239
- Filed: 2020-06-30
- Published: 2020-12-24
- Earliest claimed: 2010-09-28
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Abhijeet Ashok Chachad; Raguram Damodaran; Ramakrishnan Venkatasubramanian; Joseph Raymond Michael Zbiciak
- Web page: https://patentgrep.com/patent/US20200401532A1

## CPC

- G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA]
- G06F 1/3296: by lowering the supply or operating voltage
- G06F 7/483: Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)}
- G06F 9/3012: {Organisation of register space, e.g. banked or distributed register file}
- G06F 11/1064: {in cache or content addressable memories}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0815: Cache consistency protocols
- G06F 12/12: Replacement control
- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 13/18: based on priority control (G06F13/1605 takes precedence)
- H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply}
- H03K 21/00: Details of pulse counters or frequency dividers
- H03M 13/2903: {Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes}
- H03M 13/353: {Adaptation to the channel}
- G06F 13/1652: {in a multiprocessor architecture (interprocessor communication using common memory G06F15/167)}
- G06F 13/1657: {Access to multiple memories}
- G06F 13/1663: {Access to shared memory}
- G06F 13/364: using independent requests or grants, e.g. using separated request and grant lines
- G06F 2212/1021: Hit rate improvement
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/221: Static RAM
- G06F 2212/2532: comprising a plurality of modules
- G06F 2212/283: Plural cache memories
- G06F 2212/608: Details relating to cache mapping
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

## Claims

### Claim 1

A system-on-a-chip comprising:
a set of processing cores;
a shared memory;
an interconnect coupling the set of processing cores to the shared memory, wherein each of the set of processing cores includes:
a memory controller coupled to the interconnect that includes:
a pipeline that includes registers to store a set of transaction requests and a set of priorities associated with the set of transaction requests, wherein the pipeline is configured to provide a first transaction request of the set of transaction requests to the interconnect; and
merge logic coupled to the pipeline and configured to cause an external priority to be provided to the interconnect along with the first transaction request such that:
when a second priority associated with a second transaction request of the set of transaction requests is greater than a first priority associated with the first transaction request, cause the external priority to be based on the second priority; and
when the second priority is not greater than the first priority, cause the external priority to be based on the first priority of the first transaction request.

### Claim 2 (depends on 1)

The system-on-a-chip of claim 1, wherein:
the memory controller includes a configuration register configured to store a set of external priority values; and
the merge logic is configured to:
cause the external priority to be selected from among the set of external priority values; and
cause the configuration register to provide the external priority to the interconnect along with the first transaction request.

### Claim 3 (depends on 2)

The system-on-a-chip of claim 2, wherein the set of external priority values includes a normal priority value and an urgent priority value.

### Claim 4 (depends on 3)

The system-on-a-chip of claim 3, wherein:
the first priority of the first transaction request is associated with the normal priority value; and
the merge logic is configured to cause the urgent priority value to be selected as the external priority based on the second priority being greater than the first priority.

### Claim 5 (depends on 2)

The system-on-a-chip of claim 2, wherein:
a first core of the set of processing cores includes a level 1 cache memory; and
the merge logic of the first core is configured to cause the external priority to be selected as a highest priority of the set of external priority values based on the second transaction request including a fetch request to a branch target address from the level 1 cache memory.

### Claim 6 (depends on 2)

The system-on-a-chip of claim 2, wherein:
a first core of the set of processing cores includes a level 1 cache memory; and
the merge logic of the first core is configured to cause the external priority to be selected as a highest priority of the set of external priority values based on the second transaction request including a read allocate request from the level 1 cache memory.

### Claim 7 (depends on 2)

The system-on-a-chip of claim 2, wherein:
a first core of the set of processing cores includes a level 2 cache memory; and
the merge logic of the first core is configured to cause the external priority to be selected as a highest priority of the set of external priority values based on the second transaction request including a fetch in response to a miss in the level 2 cache memory.

### Claim 8 (depends on 1)

The system-on-a-chip of claim 1, wherein the merge logic is configured to:
determine the second transaction request to have a greatest priority from among the set of transaction requests; and
compare the first priority to the second priority based on the second transaction request having the greatest priority from among the set of transaction requests.

### Claim 9

A circuit comprising:
a core that includes a controller configured to couple the core to an interconnect, wherein the controller includes:
a pipeline component configured to:
receive a first transaction request, a first priority associated with the first transaction request, a second transaction request, and a second priority associated with the second transaction request;
store the first and second transaction requests and the first and second priorities; and
provide the first transaction request to the interconnect;
merge logic coupled to the pipeline component and configured to:
compare the first priority to the second priority; and
cause an external priority to be provided to the interconnect that is associated with the first transaction request such that:
when the second priority is greater than the first priority, cause the external priority to be based on the second priority of the second transaction request; and
when the second priority is not greater than the first priority, cause the external priority to be based on the first priority of the first transaction request.

### Claim 10 (depends on 9)

The circuit of claim 9 further comprising a configuration register configured to store a set of external priority values, wherein the merge logic is configured to:
cause the external priority to be selected from among the set of external priority values; and
cause the configuration register to provide the external priority to the interconnect along with the first transaction request.

### Claim 11 (depends on 9)

The circuit of claim 9, wherein:
the pipeline component includes a set of registers configured to store a set of transaction requests that includes the first and second transaction requests and a set of priorities that includes the first and second priorities; and
the merge logic is configured to:
determine the second transaction request to have a greatest priority from among the set of transaction requests; and
compare the first priority to the second priority based on the second transaction request having the greatest priority from among the set of transaction requests.

### Claim 12 (depends on 9)

The circuit of claim 9 further comprising a level 1 cache memory, wherein:
the external priority associated with the first transaction request is a first external priority;
the pipeline component is configured to receive a third transaction request and a fourth transaction request;
the merge logic is configured to cause a second external priority to be provided to the interconnect that is associated with the third transaction request; and
the second external priority is based on the fourth transaction request including a fetch request to a branch target address from the level 1 cache memory.

### Claim 13 (depends on 9)

The circuit of claim 9 further comprising a level 1 cache memory, wherein:
the external priority associated with the first transaction request is a first external priority;
the pipeline component is configured to receive a third transaction request and a fourth transaction request;
the merge logic is configured to cause a second external priority to be provided to the interconnect that is associated with the third transaction request; and
the second external priority is based on the fourth transaction request including a read allocate request from the level 1 cache memory.

### Claim 14 (depends on 9)

The circuit of claim 9 further comprising a level 2 cache memory, wherein:
the external priority associated with the first transaction request is a first external priority;
the pipeline component is configured to receive a third transaction request and a fourth transaction request;
the merge logic is configured to cause a second external priority to be provided to the interconnect that is associated with the third transaction request; and
the second external priority is based on the fourth transaction request including a fetch in response to a miss in the level 2 cache memory.

### Claim 15 (depends on 9)

The circuit of claim 9 further comprising a router coupled to the controller and configured to:
couple the core to a set of interconnects that includes the interconnect;
receive the first transaction request and the external priority from the controller; and
provide the first transaction request and the external priority to the interconnect based on an address of the first transaction request.

### Claim 16

A method comprising:
receiving a first transaction and a first priority associated with the first transaction;
receiving a second transaction and a second priority associated with the second transaction;
comparing the first priority to the second priority;
selecting an external priority for the first transaction based on the comparing of the first priority to the second priority such that the external priority is based on a greater of the first priority and the second priority; and
providing the first transaction and the external priority at an interconnect for transmission over the interconnect.

### Claim 17 (depends on 16)

The method of claim 16 further comprising storing a set of external priority values, wherein the selecting of the external priority for the first transaction is such that:
when the second priority is greater than the first priority, a greatest value of the set of external priority values is selected for the external priority; and
when the second priority is not greater than the first priority, a second value of the set of external priority values that is less than the greatest value is selected for the external priority.

### Claim 18 (depends on 16)

The method of claim 16 further comprising determining the second priority to be a greatest priority from among a set of priorities, wherein the comparing of the first priority to the second priority is based on the second priority being the greatest priority from among the set of priorities.

### Claim 19 (depends on 16)

The method of claim 16, wherein the external priority is a first external priority and the method further comprises:
receiving a third transaction and a fourth transaction; and
selecting a second external priority for the third transaction based on the fourth transaction including at least one of: a fetch request to a branch target address or a read allocate request.

### Claim 20 (depends on 16)

The method of claim 16, wherein the external priority is a first external priority and the method further comprises:
receiving a third transaction and a fourth transaction; and
selecting a second external priority for the third transaction based on the fourth transaction including a fetch in response to a cache miss.