# US 2020/0401530 A1 · Flatflash system for byte granularity accessibility of memory in a unified memory-storage hierarchy

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- Number: US 2020/0401530 A1
- Document ID: US20200401530A1
- Status: Published application
- Kind: A1
- Application number: 16/447,914
- Filed: 2019-06-20
- Published: 2020-12-24
- Earliest claimed: 2019-06-20
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation; University of Illinois At Urbana-Champaign
- Inventors: Ahmed ABULILA; Vikram SHARMA MAILTHODY; Zaid QURESHI; Jian HUANG; Nam SUNG KIM; Jinjun XIONG; Wen-Mei HWU
- Web page: https://patentgrep.com/patent/US20200401530A1

## CPC

- G06F 12/0893: Caches characterised by their organisation or structure
- G06F 12/1045: associated with a data cache
- G06F 12/124: {being minimized, e.g. non MRU}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 2212/1021: Hit rate improvement
- G06F 2212/225: Hybrid cache memory, e.g. having both volatile and non-volatile portions
- G06F 2212/601: Reconfiguration of cache memory
- G06F 2212/608: Details relating to cache mapping
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Various embodiments are provided for providing byte granularity accessibility of memory in a unified memory-storage hierarchy in a computing system by a processor. A location of one or more secondary memory medium pages in a secondary memory medium may be mapped into an address space of a primary memory medium to extend a memory-storage hierarchy of the secondary memory medium. The one or more secondary memory medium pages may be promoted from the secondary memory medium to the primary memory medium. The primary memory medium functions as a cache to provide byte level accessibility to the one or more primary memory medium pages. A memory request for the secondary memory medium page may be redirected using a promotion look-aside buffer (“PLB”) in a host bridge associated with the primary memory medium and the secondary memory medium.

## Claims

### Claim 1

A method, by a processor, for providing byte granularity accessibility of memory in a unified memory-storage hierarchy in a computing environment, comprising:
mapping a location of one or more secondary memory medium pages in a secondary memory medium into an address space of a primary memory medium to extend a memory-storage hierarchy of the secondary memory medium;
selectively promoting one or more secondary memory medium pages from the secondary memory medium to the primary memory medium, wherein the primary memory medium functions as a cache to provide byte level accessibility to the one or more secondary memory medium pages; and
redirecting one or more memory requests for the one or more secondary memory medium pages using a promotion look-aside buffer (“PLB”) in a host bridge associated with the primary memory medium and the secondary memory medium.

### Claim 2 (depends on 1)

The method of claim 1, further including implementing a page promotion policy in the secondary memory medium to migrate one or more frequently used secondary memory medium pages, wherein the secondary memory medium is a solid state drive (SSD) memory and the primary memory medium is a dynamic random access memory (DRAM).

### Claim 3 (depends on 1)

The method of claim 1, further including initiating a page promotion operation to promote the one or more primary memory medium pages from the secondary memory medium to the primary memory medium.

### Claim 4 (depends on 1)

The method of claim 1, further including initiating the PLB in the host bridge to redirect the one or more memory requests for the one or more secondary memory medium pages being promoted to a current location address in the one or more primary memory medium.

### Claim 5 (depends on 1)

The method of claim 1, further including selectively promoting one or more hot secondary memory medium pages from the secondary memory medium to the primary memory medium while retaining one or more cold secondary memory medium pages in the primary memory medium.

### Claim 6 (depends on 1)

The method of claim 1, further including inserting an entry into a PLB table associated with the PLB for each of the one or more secondary memory medium pages selectively promoted.

### Claim 7 (depends on 1)

The method of claim 1, further including evicting the one or more primary memory medium pages from the primary memory medium according to a least recently used (LRU) operation.

### Claim 8

A system for providing byte granularity accessibility of memory in a unified memory-storage hierarchy in a computing environment, comprising:
one or more computers with executable instructions that when executed cause the system to:
map a location of one or more secondary memory medium pages in a secondary memory medium into an address space of a primary memory medium to extend a memory-storage hierarchy of the secondary memory medium;
selectively promote one or more secondary memory medium pages from the secondary memory medium to the primary memory medium, wherein the primary memory medium functions as a cache to provide byte level accessibility to the one or more secondary memory medium pages; and
redirect one or more memory requests for the one or more secondary memory medium pages using a promotion look-aside buffer (“PLB”) in a host bridge associated with the primary memory medium and the secondary memory medium.

### Claim 9 (depends on 8)

The system of claim 8, wherein the executable instructions implement a page promotion policy in the secondary memory medium to migrate one or more frequently used secondary memory medium pages, wherein the secondary memory medium is a solid state drive (SSD) memory and the primary memory medium is a dynamic random access memory (DRAM).

### Claim 10 (depends on 8)

The system of claim 8, wherein the executable instructions initiate a page promotion operation to promote the one or more primary memory medium pages from the secondary memory medium to the primary memory medium.

### Claim 11 (depends on 8)

The system of claim 8, wherein the executable instructions initiate the PLB in the host bridge to redirect the one or more memory requests for the one or more secondary memory medium pages being promoted to a current location address in the one or more primary memory medium.

### Claim 12 (depends on 8)

The system of claim 8, wherein the executable instructions selectively promote one or more hot secondary memory medium pages from the secondary memory medium to the primary memory medium while retaining one or more cold secondary memory medium pages in the primary memory medium.

### Claim 13 (depends on 8)

The system of claim 8, wherein the executable instructions insert an entry into a PLB table associated with the PLB for each of the one or more secondary memory medium pages selectively promoted.

### Claim 14 (depends on 8)

The system of claim 8, wherein the executable instructions evict the one or more primary memory medium pages from the primary memory medium according to a least recently used (LRU) operation.

### Claim 15

A computer program product for providing byte granularity accessibility of memory in a unified memory-storage hierarchy in a computing environment by a processor, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising:
an executable portion that maps a location of one or more secondary memory medium pages in a secondary memory medium into an address space of a primary memory medium to extend a memory-storage hierarchy of the secondary memory medium;
an executable portion that selectively promotes one or more secondary memory medium pages from the secondary memory medium to the primary memory medium, wherein the primary memory medium functions as a cache to provide byte level accessibility to the one or more secondary memory medium pages; and
an executable portion that redirects one or more memory requests for the one or more secondary memory medium pages using a promotion look-aside buffer (“PLB”) in a host bridge associated with the primary memory medium and the secondary memory medium.

### Claim 16 (depends on 15)

The computer program product of claim 15, further including an executable portion that implements a page promotion policy in the secondary memory medium to migrate one or more frequently used secondary memory medium pages, wherein the secondary memory medium is a solid state drive (SSD) memory and the primary memory medium is a dynamic random access memory (DRAM).

### Claim 17 (depends on 15)

The computer program product of claim 15, further including an executable portion that a page promotion operation to promote the one or more primary memory medium pages from the secondary memory medium to the primary memory medium.

### Claim 18 (depends on 15)

The computer program product of claim 15, further including an executable portion that initiates the PLB in the host bridge to redirect the one or more memory requests for the one or more secondary memory medium pages being promoted to a current location address in the one or more primary memory medium.

### Claim 19 (depends on 15)

The computer program product of claim 15, further including an executable portion that selectively promotes one or more hot secondary memory medium pages from the secondary memory medium to the primary memory medium while retaining one or more cold secondary memory medium pages in the primary memory medium.

### Claim 20 (depends on 15)

The computer program product of claim 15, further including an executable portion that:
inserts an entry into a PLB table associated with the PLB for each of the one or more primary memory medium pages selectively promoted; or
evicts the one or more primary memory medium pages from the primary memory medium according to a least recently used (LRU) operation.